MI_example.py (10524:fff17530cef6) MI_example.py (10529:05b5a6cf3521)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 18 unchanged lines hidden (view full) ---

27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35from Ruby import send_evicts
35
36#
37# Note: the cache latency is only used by the sequencer on fast path hits
38#
39class Cache(RubyCache):
40 latency = 3
41
42def define_options(parser):

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74 assoc = options.l1d_assoc,
75 start_index_bit = block_size_bits)
76
77 #
78 # Only one unified L1 cache exists. Can cache instructions and data.
79 #
80 l1_cntrl = L1Cache_Controller(version = i,
81 cacheMemory = cache,
36
37#
38# Note: the cache latency is only used by the sequencer on fast path hits
39#
40class Cache(RubyCache):
41 latency = 3
42
43def define_options(parser):

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75 assoc = options.l1d_assoc,
76 start_index_bit = block_size_bits)
77
78 #
79 # Only one unified L1 cache exists. Can cache instructions and data.
80 #
81 l1_cntrl = L1Cache_Controller(version = i,
82 cacheMemory = cache,
82 send_evictions = (
83 options.cpu_type == "detailed"),
83 send_evictions = send_evicts(options),
84 transitions_per_cycle = options.ports,
85 clk_domain=system.cpu[i].clk_domain,
86 ruby_system = ruby_system)
87
88 cpu_seq = RubySequencer(version = i,
89 icache = cache,
90 dcache = cache,
91 clk_domain=system.cpu[i].clk_domain,

--- 87 unchanged lines hidden --- 		84 transitions_per_cycle = options.ports,
85 clk_domain=system.cpu[i].clk_domain,
86 ruby_system = ruby_system)
87
88 cpu_seq = RubySequencer(version = i,
89 icache = cache,
90 dcache = cache,
91 clk_domain=system.cpu[i].clk_domain,

--- 87 unchanged lines hidden ---