MI_example.py (10300:ed3816dae6d5) MI_example.py (10311:ad9c042dce54)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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89 icache = cache,
90 dcache = cache,
91 clk_domain=system.cpu[i].clk_domain,
92 ruby_system = ruby_system)
93
94 l1_cntrl.sequencer = cpu_seq
95 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
96
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 80 unchanged lines hidden (view full) ---

89 icache = cache,
90 dcache = cache,
91 clk_domain=system.cpu[i].clk_domain,
92 ruby_system = ruby_system)
93
94 l1_cntrl.sequencer = cpu_seq
95 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
96
97 #
98 # Add controllers and sequencers to the appropriate lists
97 # Add controllers and sequencers to the appropriate lists
99 #
100 cpu_sequencers.append(cpu_seq)
101 l1_cntrl_nodes.append(l1_cntrl)
102
98 cpu_sequencers.append(cpu_seq)
99 l1_cntrl_nodes.append(l1_cntrl)
100
101 # Connect the L1 controllers and the network
102 l1_cntrl.requestFromCache = ruby_system.network.slave
103 l1_cntrl.responseFromCache = ruby_system.network.slave
104 l1_cntrl.forwardToCache = ruby_system.network.master
105 l1_cntrl.responseToCache = ruby_system.network.master
106
107
103 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
104 assert(phys_mem_size % options.num_dirs == 0)
105 mem_module_size = phys_mem_size / options.num_dirs
106
107 # Run each of the ruby memory controllers at a ratio of the frequency of
108 # the ruby system.
109 # clk_divider value is a fix to pass regression.
110 ruby_system.memctrl_clk_domain = DerivedClockDomain(

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134 options.map_levels),
135 memBuffer = mem_cntrl,
136 transitions_per_cycle = options.ports,
137 ruby_system = ruby_system)
138
139 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
140 dir_cntrl_nodes.append(dir_cntrl)
141
108 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
109 assert(phys_mem_size % options.num_dirs == 0)
110 mem_module_size = phys_mem_size / options.num_dirs
111
112 # Run each of the ruby memory controllers at a ratio of the frequency of
113 # the ruby system.
114 # clk_divider value is a fix to pass regression.
115 ruby_system.memctrl_clk_domain = DerivedClockDomain(

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139 options.map_levels),
140 memBuffer = mem_cntrl,
141 transitions_per_cycle = options.ports,
142 ruby_system = ruby_system)
143
144 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
145 dir_cntrl_nodes.append(dir_cntrl)
146
147 # Connect the directory controllers and the network
148 dir_cntrl.requestToDir = ruby_system.network.master
149 dir_cntrl.dmaRequestToDir = ruby_system.network.master
150
151 dir_cntrl.responseFromDir = ruby_system.network.slave
152 dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
153 dir_cntrl.forwardFromDir = ruby_system.network.slave
154
155
142 for i, dma_port in enumerate(dma_ports):
143 #
144 # Create the Ruby objects associated with the dma controller
145 #
146 dma_seq = DMASequencer(version = i,
147 ruby_system = ruby_system)
148
149 dma_cntrl = DMA_Controller(version = i,
150 dma_sequencer = dma_seq,
151 transitions_per_cycle = options.ports,
152 ruby_system = ruby_system)
153
154 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
155 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
156 dma_cntrl_nodes.append(dma_cntrl)
157
156 for i, dma_port in enumerate(dma_ports):
157 #
158 # Create the Ruby objects associated with the dma controller
159 #
160 dma_seq = DMASequencer(version = i,
161 ruby_system = ruby_system)
162
163 dma_cntrl = DMA_Controller(version = i,
164 dma_sequencer = dma_seq,
165 transitions_per_cycle = options.ports,
166 ruby_system = ruby_system)
167
168 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
169 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
170 dma_cntrl_nodes.append(dma_cntrl)
171
158 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
172 # Connect the directory controllers and the network
173 dma_cntrl.requestToDir = ruby_system.network.master
174 dma_cntrl.responseFromDir = ruby_system.network.slave
159
175
160 topology = create_topology(all_cntrls, options)
161
176
177 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
178 topology = create_topology(all_cntrls, options)
162 return (cpu_sequencers, dir_cntrl_nodes, topology)
179 return (cpu_sequencers, dir_cntrl_nodes, topology)