MI_example.py (10116:d61a59beb670) MI_example.py (10300:ed3816dae6d5)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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77 #
78 # Only one unified L1 cache exists. Can cache instructions and data.
79 #
80 l1_cntrl = L1Cache_Controller(version = i,
81 cacheMemory = cache,
82 send_evictions = (
83 options.cpu_type == "detailed"),
84 transitions_per_cycle = options.ports,
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 68 unchanged lines hidden (view full) ---

77 #
78 # Only one unified L1 cache exists. Can cache instructions and data.
79 #
80 l1_cntrl = L1Cache_Controller(version = i,
81 cacheMemory = cache,
82 send_evictions = (
83 options.cpu_type == "detailed"),
84 transitions_per_cycle = options.ports,
85 clk_domain=system.cpu[i].clk_domain,
85 ruby_system = ruby_system)
86
87 cpu_seq = RubySequencer(version = i,
88 icache = cache,
89 dcache = cache,
86 ruby_system = ruby_system)
87
88 cpu_seq = RubySequencer(version = i,
89 icache = cache,
90 dcache = cache,
91 clk_domain=system.cpu[i].clk_domain,
90 ruby_system = ruby_system)
91
92 l1_cntrl.sequencer = cpu_seq
93 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
94
95 #
96 # Add controllers and sequencers to the appropriate lists
97 #

--- 63 unchanged lines hidden --- 		92 ruby_system = ruby_system)
93
94 l1_cntrl.sequencer = cpu_seq
95 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
96
97 #
98 # Add controllers and sequencers to the appropriate lists
99 #

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