MI_example.py (10092:c0db268f811b) MI_example.py (10116:d61a59beb670)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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37# Note: the cache latency is only used by the sequencer on fast path hits
38#
39class Cache(RubyCache):
40 latency = 3
41
42def define_options(parser):
43 return
44
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 28 unchanged lines hidden (view full) ---

37# Note: the cache latency is only used by the sequencer on fast path hits
38#
39class Cache(RubyCache):
40 latency = 3
41
42def define_options(parser):
43 return
44
45def create_system(options, system, piobus, dma_ports, ruby_system):
45def create_system(options, system, dma_ports, ruby_system):
46
47 if buildEnv['PROTOCOL'] != 'MI_example':
48 panic("This script requires the MI_example protocol to be built.")
49
50 cpu_sequencers = []
51
52 #
53 # The ruby network creation expects the list of nodes in the system to be

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85 ruby_system = ruby_system)
86
87 cpu_seq = RubySequencer(version = i,
88 icache = cache,
89 dcache = cache,
90 ruby_system = ruby_system)
91
92 l1_cntrl.sequencer = cpu_seq
46
47 if buildEnv['PROTOCOL'] != 'MI_example':
48 panic("This script requires the MI_example protocol to be built.")
49
50 cpu_sequencers = []
51
52 #
53 # The ruby network creation expects the list of nodes in the system to be

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85 ruby_system = ruby_system)
86
87 cpu_seq = RubySequencer(version = i,
88 icache = cache,
89 dcache = cache,
90 ruby_system = ruby_system)
91
92 l1_cntrl.sequencer = cpu_seq
93
94 if piobus != None:
95 cpu_seq.pio_master_port = piobus.slave
96 cpu_seq.mem_master_port = piobus.slave
97 cpu_seq.pio_slave_port = piobus.master
98
99 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
93 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
94
100 #
101 # Add controllers and sequencers to the appropriate lists
102 #
103 cpu_sequencers.append(cpu_seq)
104 l1_cntrl_nodes.append(l1_cntrl)
105
106 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
107 assert(phys_mem_size % options.num_dirs == 0)

--- 58 unchanged lines hidden --- 		95 #
96 # Add controllers and sequencers to the appropriate lists
97 #
98 cpu_sequencers.append(cpu_seq)
99 l1_cntrl_nodes.append(l1_cntrl)
100
101 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
102 assert(phys_mem_size % options.num_dirs == 0)

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