1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 91 unchanged lines hidden (view full) --- 100 # 101 # Add controllers and sequencers to the appropriate lists 102 # 103 cpu_sequencers.append(cpu_seq) 104 l1_cntrl_nodes.append(l1_cntrl) 105 106 cntrl_count += 1 107 |
108 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) |
109 assert(phys_mem_size % options.num_dirs == 0) 110 mem_module_size = phys_mem_size / options.num_dirs 111 112 # Run each of the ruby memory controllers at a ratio of the frequency of 113 # the ruby system. 114 # clk_divider value is a fix to pass regression. 115 ruby_system.memctrl_clk_domain = DerivedClockDomain( 116 clk_domain=ruby_system.clk_domain, --- 54 unchanged lines hidden --- |