1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 91 unchanged lines hidden (view full) --- 100 # 101 # Add controllers and sequencers to the appropriate lists 102 # 103 cpu_sequencers.append(cpu_seq) 104 l1_cntrl_nodes.append(l1_cntrl) 105 106 cntrl_count += 1 107 |
108 phys_mem_size = sum(map(lambda mem: mem.range.size(), 109 system.memories.unproxy(system))) |
110 mem_module_size = phys_mem_size / options.num_dirs 111 112 for i in xrange(options.num_dirs): 113 # 114 # Create the Ruby objects associated with the directory controller 115 # 116 117 mem_cntrl = RubyMemoryControl(version = i, --- 44 unchanged lines hidden --- |