1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 64 unchanged lines hidden (view full) --- 73 # 74 cache = Cache(size = options.l1d_size, 75 assoc = options.l1d_assoc, 76 start_index_bit = block_size_bits) 77 78 # 79 # Only one unified L1 cache exists. Can cache instructions and data. 80 # |
81 l1_cntrl = L1Cache_Controller(version = i, 82 cntrl_id = cntrl_count, 83 cacheMemory = cache) 84 |
85 cpu_seq = RubySequencer(version = i, 86 icache = cache, 87 dcache = cache, 88 physMemPort = system.physmem.port, 89 physmem = system.physmem) 90 |
91 l1_cntrl.sequencer = cpu_seq 92 |
93 if piobus != None: 94 cpu_seq.pio_port = piobus.port 95 |
96 exec("system.l1_cntrl%d = l1_cntrl" % i) 97 # 98 # Add controllers and sequencers to the appropriate lists 99 # 100 cpu_sequencers.append(cpu_seq) 101 l1_cntrl_nodes.append(l1_cntrl) 102 103 cntrl_count += 1 --- 56 unchanged lines hidden --- |