1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 140 unchanged lines hidden (view full) --- 149 transitions_per_cycle = options.ports, 150 ruby_system = ruby_system) 151 152 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 153 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 154 dma_cntrl_nodes.append(dma_cntrl) 155 156 # Connect the directory controllers and the network |
157 dma_cntrl.requestToDir = ruby_system.network.slave 158 dma_cntrl.responseFromDir = ruby_system.network.master |
159 160 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 161 162 # Create the io controller and the sequencer 163 if full_system: 164 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 165 ruby_system._io_port = io_seq 166 io_controller = DMA_Controller(version = len(dma_ports), --- 12 unchanged lines hidden --- |