1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 68 unchanged lines hidden (view full) --- 77 # 78 # Only one unified L1 cache exists. Can cache instructions and data. 79 # 80 l1_cntrl = L1Cache_Controller(version = i, 81 cacheMemory = cache, 82 send_evictions = ( 83 options.cpu_type == "detailed"), 84 transitions_per_cycle = options.ports, |
85 clk_domain=system.cpu[i].clk_domain, |
86 ruby_system = ruby_system) 87 88 cpu_seq = RubySequencer(version = i, 89 icache = cache, 90 dcache = cache, |
91 clk_domain=system.cpu[i].clk_domain, |
92 ruby_system = ruby_system) 93 94 l1_cntrl.sequencer = cpu_seq 95 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 96 97 # 98 # Add controllers and sequencers to the appropriate lists 99 # --- 63 unchanged lines hidden --- |