1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 28 unchanged lines hidden (view full) --- 37# Note: the cache latency is only used by the sequencer on fast path hits 38# 39class Cache(RubyCache): 40 latency = 3 41 42def define_options(parser): 43 return 44 |
45def create_system(options, system, dma_ports, ruby_system): |
46 47 if buildEnv['PROTOCOL'] != 'MI_example': 48 panic("This script requires the MI_example protocol to be built.") 49 50 cpu_sequencers = [] 51 52 # 53 # The ruby network creation expects the list of nodes in the system to be --- 31 unchanged lines hidden (view full) --- 85 ruby_system = ruby_system) 86 87 cpu_seq = RubySequencer(version = i, 88 icache = cache, 89 dcache = cache, 90 ruby_system = ruby_system) 91 92 l1_cntrl.sequencer = cpu_seq |
93 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) |
94 |
95 # 96 # Add controllers and sequencers to the appropriate lists 97 # 98 cpu_sequencers.append(cpu_seq) 99 l1_cntrl_nodes.append(l1_cntrl) 100 101 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 102 assert(phys_mem_size % options.num_dirs == 0) --- 58 unchanged lines hidden --- |