1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 78 unchanged lines hidden (view full) --- 87 cpu_seq = RubySequencer(version = i, 88 icache = cache, 89 dcache = cache, 90 ruby_system = ruby_system) 91 92 l1_cntrl.sequencer = cpu_seq 93 94 if piobus != None: |
95 cpu_seq.pio_master_port = piobus.slave 96 cpu_seq.mem_master_port = piobus.slave 97 cpu_seq.pio_slave_port = piobus.master |
98 99 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 100 # 101 # Add controllers and sequencers to the appropriate lists 102 # 103 cpu_sequencers.append(cpu_seq) 104 l1_cntrl_nodes.append(l1_cntrl) 105 --- 60 unchanged lines hidden --- |