80a81,84
> l1_cntrl = L1Cache_Controller(version = i,
> cntrl_id = cntrl_count,
> cacheMemory = cache)
>
86a91,92
> l1_cntrl.sequencer = cpu_seq
>
90,94d95
< l1_cntrl = L1Cache_Controller(version = i,
< cntrl_id = cntrl_count,
< sequencer = cpu_seq,
< cacheMemory = cache)
<