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< #
< # Only one unified L1 cache exists. Can cache instructions and data.
< #
< l1_cntrl = L1Cache_Controller(version = i,
< cacheMemory = cache,
< send_evictions = send_evicts(options),
< transitions_per_cycle = options.ports,
< clk_domain=system.cpu[i].clk_domain,
< ruby_system = ruby_system)
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< cpu_seq = RubySequencer(version = i,
< icache = cache,
< dcache = cache,
< clk_domain=system.cpu[i].clk_domain,
< ruby_system = ruby_system)
---
> # the ruby random tester reuses num_cpus to specify the
> # number of cpu ports connected to the tester object, which
> # is stored in system.cpu. because there is only ever one
> # tester object, num_cpus is not necessarily equal to the
> # size of system.cpu; therefore if len(system.cpu) == 1
> # we use system.cpu[0] to set the clk_domain, thereby ensuring
> # we don't index off the end of the cpu list.
> if len(system.cpu) == 1:
> clk_domain = system.cpu[0].clk_domain
> else:
> clk_domain = system.cpu[i].clk_domain
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> # Only one unified L1 cache exists. Can cache instructions and data.
> l1_cntrl = L1Cache_Controller(version=i, cacheMemory=cache,
> send_evictions=send_evicts(options),
> transitions_per_cycle=options.ports,
> clk_domain=clk_domain,
> ruby_system=ruby_system)
>
> cpu_seq = RubySequencer(version=i, icache=cache, dcache=cache,
> clk_domain=clk_domain, ruby_system=ruby_system)
>