1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34
35#
36# Note: the cache latency is only used by the sequencer on fast path hits
37#
38class Cache(RubyCache):
39 latency = 3
40
41def define_options(parser):
42 return
43
44def create_system(options, system, piobus, dma_devices):
45
46 if buildEnv['PROTOCOL'] != 'MI_example':
47 panic("This script requires the MI_example protocol to be built.")
48
49 cpu_sequencers = []
50
51 #
52 # The ruby network creation expects the list of nodes in the system to be
53 # consistent with the NetDest list. Therefore the l1 controller nodes must be
54 # listed before the directory nodes and directory nodes before dma nodes, etc.
55 #
56 l1_cntrl_nodes = []
57 dir_cntrl_nodes = []
58 dma_cntrl_nodes = []
59
60 #
61 # Must create the individual controllers before the network to ensure the
62 # controller constructors are called before the network constructor
63 #
64 block_size_bits = int(math.log(options.cacheline_size, 2))
65
66 cntrl_count = 0
67
68 for i in xrange(options.num_cpus):
69 #
70 # First create the Ruby objects associated with this cpu
71 # Only one cache exists for this protocol, so by default use the L1D
72 # config parameters.
73 #
74 cache = Cache(size = options.l1d_size,
75 assoc = options.l1d_assoc,
76 start_index_bit = block_size_bits)
77
78 #
79 # Only one unified L1 cache exists. Can cache instructions and data.
80 #
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34
35#
36# Note: the cache latency is only used by the sequencer on fast path hits
37#
38class Cache(RubyCache):
39 latency = 3
40
41def define_options(parser):
42 return
43
44def create_system(options, system, piobus, dma_devices):
45
46 if buildEnv['PROTOCOL'] != 'MI_example':
47 panic("This script requires the MI_example protocol to be built.")
48
49 cpu_sequencers = []
50
51 #
52 # The ruby network creation expects the list of nodes in the system to be
53 # consistent with the NetDest list. Therefore the l1 controller nodes must be
54 # listed before the directory nodes and directory nodes before dma nodes, etc.
55 #
56 l1_cntrl_nodes = []
57 dir_cntrl_nodes = []
58 dma_cntrl_nodes = []
59
60 #
61 # Must create the individual controllers before the network to ensure the
62 # controller constructors are called before the network constructor
63 #
64 block_size_bits = int(math.log(options.cacheline_size, 2))
65
66 cntrl_count = 0
67
68 for i in xrange(options.num_cpus):
69 #
70 # First create the Ruby objects associated with this cpu
71 # Only one cache exists for this protocol, so by default use the L1D
72 # config parameters.
73 #
74 cache = Cache(size = options.l1d_size,
75 assoc = options.l1d_assoc,
76 start_index_bit = block_size_bits)
77
78 #
79 # Only one unified L1 cache exists. Can cache instructions and data.
80 #
|
| 81 l1_cntrl = L1Cache_Controller(version = i,
82 cntrl_id = cntrl_count,
83 cacheMemory = cache)
84
|
81 cpu_seq = RubySequencer(version = i,
82 icache = cache,
83 dcache = cache,
84 physMemPort = system.physmem.port,
85 physmem = system.physmem)
86
| 85 cpu_seq = RubySequencer(version = i,
86 icache = cache,
87 dcache = cache,
88 physMemPort = system.physmem.port,
89 physmem = system.physmem)
90
|
| 91 l1_cntrl.sequencer = cpu_seq
92
|
87 if piobus != None:
88 cpu_seq.pio_port = piobus.port
89
| 93 if piobus != None:
94 cpu_seq.pio_port = piobus.port
95
|
90 l1_cntrl = L1Cache_Controller(version = i,
91 cntrl_id = cntrl_count,
92 sequencer = cpu_seq,
93 cacheMemory = cache)
94
| |
95 exec("system.l1_cntrl%d = l1_cntrl" % i)
96 #
97 # Add controllers and sequencers to the appropriate lists
98 #
99 cpu_sequencers.append(cpu_seq)
100 l1_cntrl_nodes.append(l1_cntrl)
101
102 cntrl_count += 1
103
104 phys_mem_size = long(system.physmem.range.second) - \
105 long(system.physmem.range.first) + 1
106 mem_module_size = phys_mem_size / options.num_dirs
107
108 for i in xrange(options.num_dirs):
109 #
110 # Create the Ruby objects associated with the directory controller
111 #
112
113 mem_cntrl = RubyMemoryControl(version = i)
114
115 dir_size = MemorySize('0B')
116 dir_size.value = mem_module_size
117
118 dir_cntrl = Directory_Controller(version = i,
119 cntrl_id = cntrl_count,
120 directory = \
121 RubyDirectoryMemory( \
122 version = i,
123 size = dir_size,
124 use_map = options.use_map,
125 map_levels = \
126 options.map_levels),
127 memBuffer = mem_cntrl)
128
129 exec("system.dir_cntrl%d = dir_cntrl" % i)
130 dir_cntrl_nodes.append(dir_cntrl)
131
132 cntrl_count += 1
133
134 for i, dma_device in enumerate(dma_devices):
135 #
136 # Create the Ruby objects associated with the dma controller
137 #
138 dma_seq = DMASequencer(version = i,
139 physMemPort = system.physmem.port,
140 physmem = system.physmem)
141
142 dma_cntrl = DMA_Controller(version = i,
143 cntrl_id = cntrl_count,
144 dma_sequencer = dma_seq)
145
146 exec("system.dma_cntrl%d = dma_cntrl" % i)
147 if dma_device.type == 'MemTest':
148 system.dma_cntrl.dma_sequencer.port = dma_device.test
149 else:
150 system.dma_cntrl.dma_sequencer.port = dma_device.dma
151 dma_cntrl.dma_sequencer.port = dma_device.dma
152 dma_cntrl_nodes.append(dma_cntrl)
153
154 cntrl_count += 1
155
156 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
157
158 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
| 96 exec("system.l1_cntrl%d = l1_cntrl" % i)
97 #
98 # Add controllers and sequencers to the appropriate lists
99 #
100 cpu_sequencers.append(cpu_seq)
101 l1_cntrl_nodes.append(l1_cntrl)
102
103 cntrl_count += 1
104
105 phys_mem_size = long(system.physmem.range.second) - \
106 long(system.physmem.range.first) + 1
107 mem_module_size = phys_mem_size / options.num_dirs
108
109 for i in xrange(options.num_dirs):
110 #
111 # Create the Ruby objects associated with the directory controller
112 #
113
114 mem_cntrl = RubyMemoryControl(version = i)
115
116 dir_size = MemorySize('0B')
117 dir_size.value = mem_module_size
118
119 dir_cntrl = Directory_Controller(version = i,
120 cntrl_id = cntrl_count,
121 directory = \
122 RubyDirectoryMemory( \
123 version = i,
124 size = dir_size,
125 use_map = options.use_map,
126 map_levels = \
127 options.map_levels),
128 memBuffer = mem_cntrl)
129
130 exec("system.dir_cntrl%d = dir_cntrl" % i)
131 dir_cntrl_nodes.append(dir_cntrl)
132
133 cntrl_count += 1
134
135 for i, dma_device in enumerate(dma_devices):
136 #
137 # Create the Ruby objects associated with the dma controller
138 #
139 dma_seq = DMASequencer(version = i,
140 physMemPort = system.physmem.port,
141 physmem = system.physmem)
142
143 dma_cntrl = DMA_Controller(version = i,
144 cntrl_id = cntrl_count,
145 dma_sequencer = dma_seq)
146
147 exec("system.dma_cntrl%d = dma_cntrl" % i)
148 if dma_device.type == 'MemTest':
149 system.dma_cntrl.dma_sequencer.port = dma_device.test
150 else:
151 system.dma_cntrl.dma_sequencer.port = dma_device.dma
152 dma_cntrl.dma_sequencer.port = dma_device.dma
153 dma_cntrl_nodes.append(dma_cntrl)
154
155 cntrl_count += 1
156
157 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
158
159 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
|