1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import m5
31from m5.objects import *
32from m5.defines import buildEnv
33
34#
35# Note: the cache latency is only used by the sequencer on fast path hits
36#
37class Cache(RubyCache):
38 latency = 3
39
40def define_options(parser):
41 return
42
43def create_system(options, system, piobus, dma_devices):
44
45 if buildEnv['PROTOCOL'] != 'MI_example':
46 panic("This script requires the MI_example protocol to be built.")
47
48 cpu_sequencers = []
49
50 #
51 # The ruby network creation expects the list of nodes in the system to be
52 # consistent with the NetDest list. Therefore the l1 controller nodes must be
53 # listed before the directory nodes and directory nodes before dma nodes, etc.
54 #
55 l1_cntrl_nodes = []
56 dir_cntrl_nodes = []
57 dma_cntrl_nodes = []
58
59 #
60 # Must create the individual controllers before the network to ensure the
61 # controller constructors are called before the network constructor
62 #
63
64 for i in xrange(options.num_cpus):
65 #
66 # First create the Ruby objects associated with this cpu
67 # Only one cache exists for this protocol, so by default use the L1D
68 # config parameters.
69 #
70 cache = Cache(size = options.l1d_size,
71 assoc = options.l1d_assoc)
72
73 #
74 # Only one unified L1 cache exists. Can cache instructions and data.
75 #
76 cpu_seq = RubySequencer(version = i,
77 icache = cache,
78 dcache = cache,
79 physMemPort = system.physmem.port,
80 physmem = system.physmem)
81
82 if piobus != None:
83 cpu_seq.pio_port = piobus.port
84
85 l1_cntrl = L1Cache_Controller(version = i,
86 sequencer = cpu_seq,
87 cacheMemory = cache)
88
89 exec("system.l1_cntrl%d = l1_cntrl" % i)
90 #
91 # Add controllers and sequencers to the appropriate lists
92 #
93 cpu_sequencers.append(cpu_seq)
94 l1_cntrl_nodes.append(l1_cntrl)
95
96 phys_mem_size = long(system.physmem.range.second) - \
97 long(system.physmem.range.first) + 1
98 mem_module_size = phys_mem_size / options.num_dirs
99
100 for i in xrange(options.num_dirs):
101 #
102 # Create the Ruby objects associated with the directory controller
103 #
104
105 mem_cntrl = RubyMemoryControl(version = i)
106
107 dir_size = MemorySize('0B')
108 dir_size.value = mem_module_size
109
110 dir_cntrl = Directory_Controller(version = i,
111 directory = \
112 RubyDirectoryMemory( \
113 version = i,
114 size = dir_size,
115 use_map = options.use_map,
116 map_levels = \
117 options.map_levels),
118 memBuffer = mem_cntrl)
119
120 exec("system.dir_cntrl%d = dir_cntrl" % i)
121 dir_cntrl_nodes.append(dir_cntrl)
122
123 for i, dma_device in enumerate(dma_devices):
124 #
125 # Create the Ruby objects associated with the dma controller
126 #
127 dma_seq = DMASequencer(version = i,
128 physMemPort = system.physmem.port,
129 physmem = system.physmem)
130
131 dma_cntrl = DMA_Controller(version = i,
132 dma_sequencer = dma_seq)
133
134 exec("system.dma_cntrl%d = dma_cntrl" % i)
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import m5
31from m5.objects import *
32from m5.defines import buildEnv
33
34#
35# Note: the cache latency is only used by the sequencer on fast path hits
36#
37class Cache(RubyCache):
38 latency = 3
39
40def define_options(parser):
41 return
42
43def create_system(options, system, piobus, dma_devices):
44
45 if buildEnv['PROTOCOL'] != 'MI_example':
46 panic("This script requires the MI_example protocol to be built.")
47
48 cpu_sequencers = []
49
50 #
51 # The ruby network creation expects the list of nodes in the system to be
52 # consistent with the NetDest list. Therefore the l1 controller nodes must be
53 # listed before the directory nodes and directory nodes before dma nodes, etc.
54 #
55 l1_cntrl_nodes = []
56 dir_cntrl_nodes = []
57 dma_cntrl_nodes = []
58
59 #
60 # Must create the individual controllers before the network to ensure the
61 # controller constructors are called before the network constructor
62 #
63
64 for i in xrange(options.num_cpus):
65 #
66 # First create the Ruby objects associated with this cpu
67 # Only one cache exists for this protocol, so by default use the L1D
68 # config parameters.
69 #
70 cache = Cache(size = options.l1d_size,
71 assoc = options.l1d_assoc)
72
73 #
74 # Only one unified L1 cache exists. Can cache instructions and data.
75 #
76 cpu_seq = RubySequencer(version = i,
77 icache = cache,
78 dcache = cache,
79 physMemPort = system.physmem.port,
80 physmem = system.physmem)
81
82 if piobus != None:
83 cpu_seq.pio_port = piobus.port
84
85 l1_cntrl = L1Cache_Controller(version = i,
86 sequencer = cpu_seq,
87 cacheMemory = cache)
88
89 exec("system.l1_cntrl%d = l1_cntrl" % i)
90 #
91 # Add controllers and sequencers to the appropriate lists
92 #
93 cpu_sequencers.append(cpu_seq)
94 l1_cntrl_nodes.append(l1_cntrl)
95
96 phys_mem_size = long(system.physmem.range.second) - \
97 long(system.physmem.range.first) + 1
98 mem_module_size = phys_mem_size / options.num_dirs
99
100 for i in xrange(options.num_dirs):
101 #
102 # Create the Ruby objects associated with the directory controller
103 #
104
105 mem_cntrl = RubyMemoryControl(version = i)
106
107 dir_size = MemorySize('0B')
108 dir_size.value = mem_module_size
109
110 dir_cntrl = Directory_Controller(version = i,
111 directory = \
112 RubyDirectoryMemory( \
113 version = i,
114 size = dir_size,
115 use_map = options.use_map,
116 map_levels = \
117 options.map_levels),
118 memBuffer = mem_cntrl)
119
120 exec("system.dir_cntrl%d = dir_cntrl" % i)
121 dir_cntrl_nodes.append(dir_cntrl)
122
123 for i, dma_device in enumerate(dma_devices):
124 #
125 # Create the Ruby objects associated with the dma controller
126 #
127 dma_seq = DMASequencer(version = i,
128 physMemPort = system.physmem.port,
129 physmem = system.physmem)
130
131 dma_cntrl = DMA_Controller(version = i,
132 dma_sequencer = dma_seq)
133
134 exec("system.dma_cntrl%d = dma_cntrl" % i)
|