1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import m5
31from m5.objects import *
32from m5.defines import buildEnv
33from m5.util import addToPath
34
35#
36# Note: the cache latency is only used by the sequencer on fast path hits
37#
38class Cache(RubyCache):
39 latency = 3
40
41def create_system(options, phys_mem, piobus, dma_devices):
42
43 if buildEnv['PROTOCOL'] != 'MI_example':
44 panic("This script requires the MI_example protocol to be built.")
45
46 cpu_sequencers = []
47
48 #
49 # The ruby network creation expects the list of nodes in the system to be
50 # consistent with the NetDest list. Therefore the l1 controller nodes must be
51 # listed before the directory nodes and directory nodes before dma nodes, etc.
52 #
53 l1_cntrl_nodes = []
54 dir_cntrl_nodes = []
55 dma_cntrl_nodes = []
56
57 #
58 # Must create the individual controllers before the network to ensure the
59 # controller constructors are called before the network constructor
60 #
61
62 for i in xrange(options.num_cpus):
63 #
64 # First create the Ruby objects associated with this cpu
65 # Only one cache exists for this protocol, so by default use the L1D
66 # config parameters.
67 #
68 cache = Cache(size = options.l1d_size,
69 assoc = options.l1d_assoc)
70
71 #
72 # Only one unified L1 cache exists. Can cache instructions and data.
73 #
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import m5
31from m5.objects import *
32from m5.defines import buildEnv
33from m5.util import addToPath
34
35#
36# Note: the cache latency is only used by the sequencer on fast path hits
37#
38class Cache(RubyCache):
39 latency = 3
40
41def create_system(options, phys_mem, piobus, dma_devices):
42
43 if buildEnv['PROTOCOL'] != 'MI_example':
44 panic("This script requires the MI_example protocol to be built.")
45
46 cpu_sequencers = []
47
48 #
49 # The ruby network creation expects the list of nodes in the system to be
50 # consistent with the NetDest list. Therefore the l1 controller nodes must be
51 # listed before the directory nodes and directory nodes before dma nodes, etc.
52 #
53 l1_cntrl_nodes = []
54 dir_cntrl_nodes = []
55 dma_cntrl_nodes = []
56
57 #
58 # Must create the individual controllers before the network to ensure the
59 # controller constructors are called before the network constructor
60 #
61
62 for i in xrange(options.num_cpus):
63 #
64 # First create the Ruby objects associated with this cpu
65 # Only one cache exists for this protocol, so by default use the L1D
66 # config parameters.
67 #
68 cache = Cache(size = options.l1d_size,
69 assoc = options.l1d_assoc)
70
71 #
72 # Only one unified L1 cache exists. Can cache instructions and data.
73 #
|
75 dcache = cache,
76 physMemPort = phys_mem.port,
77 physmem = phys_mem)
78
79 if piobus != None:
80 cpu_seq.pio_port = piobus.port
81
82 l1_cntrl = L1Cache_Controller(version = i,
83 sequencer = cpu_seq,
84 cacheMemory = cache)
85 #
86 # Add controllers and sequencers to the appropriate lists
87 #
88 cpu_sequencers.append(cpu_seq)
89 l1_cntrl_nodes.append(l1_cntrl)
90
91 phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
92 mem_module_size = phys_mem_size / options.num_dirs
93
94 for i in xrange(options.num_dirs):
95 #
96 # Create the Ruby objects associated with the directory controller
97 #
98
99 mem_cntrl = RubyMemoryControl(version = i)
100
101 dir_size = MemorySize('0B')
102 dir_size.value = mem_module_size
103
104 dir_cntrl = Directory_Controller(version = i,
105 directory = \
106 RubyDirectoryMemory(version = i,
107 size = dir_size),
108 memBuffer = mem_cntrl)
109
110 dir_cntrl_nodes.append(dir_cntrl)
111
112 for i, dma_device in enumerate(dma_devices):
113 #
114 # Create the Ruby objects associated with the dma controller
115 #
116 dma_seq = DMASequencer(version = i,
117 physMemPort = phys_mem.port,
118 physmem = phys_mem)
119
120 dma_cntrl = DMA_Controller(version = i,
121 dma_sequencer = dma_seq)
122
123 dma_cntrl.dma_sequencer.port = dma_device.dma
124 dma_cntrl_nodes.append(dma_cntrl)
125
126 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
127
128 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
| 76 dcache = cache,
77 physMemPort = phys_mem.port,
78 physmem = phys_mem)
79
80 if piobus != None:
81 cpu_seq.pio_port = piobus.port
82
83 l1_cntrl = L1Cache_Controller(version = i,
84 sequencer = cpu_seq,
85 cacheMemory = cache)
86 #
87 # Add controllers and sequencers to the appropriate lists
88 #
89 cpu_sequencers.append(cpu_seq)
90 l1_cntrl_nodes.append(l1_cntrl)
91
92 phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
93 mem_module_size = phys_mem_size / options.num_dirs
94
95 for i in xrange(options.num_dirs):
96 #
97 # Create the Ruby objects associated with the directory controller
98 #
99
100 mem_cntrl = RubyMemoryControl(version = i)
101
102 dir_size = MemorySize('0B')
103 dir_size.value = mem_module_size
104
105 dir_cntrl = Directory_Controller(version = i,
106 directory = \
107 RubyDirectoryMemory(version = i,
108 size = dir_size),
109 memBuffer = mem_cntrl)
110
111 dir_cntrl_nodes.append(dir_cntrl)
112
113 for i, dma_device in enumerate(dma_devices):
114 #
115 # Create the Ruby objects associated with the dma controller
116 #
117 dma_seq = DMASequencer(version = i,
118 physMemPort = phys_mem.port,
119 physmem = phys_mem)
120
121 dma_cntrl = DMA_Controller(version = i,
122 dma_sequencer = dma_seq)
123
124 dma_cntrl.dma_sequencer.port = dma_device.dma
125 dma_cntrl_nodes.append(dma_cntrl)
126
127 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
128
129 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
|