1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35from Ruby import send_evicts
36
37#
38# Declare caches used by the protocol
39#
40class L1Cache(RubyCache): pass
41
42def define_options(parser):
43 return
44
45def create_system(options, full_system, system, dma_ports, ruby_system):
46
47 if buildEnv['PROTOCOL'] != 'MI_example':
48 panic("This script requires the MI_example protocol to be built.")
49
50 cpu_sequencers = []
51
52 #
53 # The ruby network creation expects the list of nodes in the system to be
54 # consistent with the NetDest list. Therefore the l1 controller nodes must be
55 # listed before the directory nodes and directory nodes before dma nodes, etc.
56 #
57 l1_cntrl_nodes = []
58 dir_cntrl_nodes = []
59 dma_cntrl_nodes = []
60
61 #
62 # Must create the individual controllers before the network to ensure the
63 # controller constructors are called before the network constructor
64 #
65 block_size_bits = int(math.log(options.cacheline_size, 2))
66
67 for i in xrange(options.num_cpus):
68 #
69 # First create the Ruby objects associated with this cpu
70 # Only one cache exists for this protocol, so by default use the L1D
71 # config parameters.
72 #
73 cache = L1Cache(size = options.l1d_size,
74 assoc = options.l1d_assoc,
75 start_index_bit = block_size_bits)
76
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35from Ruby import send_evicts
36
37#
38# Declare caches used by the protocol
39#
40class L1Cache(RubyCache): pass
41
42def define_options(parser):
43 return
44
45def create_system(options, full_system, system, dma_ports, ruby_system):
46
47 if buildEnv['PROTOCOL'] != 'MI_example':
48 panic("This script requires the MI_example protocol to be built.")
49
50 cpu_sequencers = []
51
52 #
53 # The ruby network creation expects the list of nodes in the system to be
54 # consistent with the NetDest list. Therefore the l1 controller nodes must be
55 # listed before the directory nodes and directory nodes before dma nodes, etc.
56 #
57 l1_cntrl_nodes = []
58 dir_cntrl_nodes = []
59 dma_cntrl_nodes = []
60
61 #
62 # Must create the individual controllers before the network to ensure the
63 # controller constructors are called before the network constructor
64 #
65 block_size_bits = int(math.log(options.cacheline_size, 2))
66
67 for i in xrange(options.num_cpus):
68 #
69 # First create the Ruby objects associated with this cpu
70 # Only one cache exists for this protocol, so by default use the L1D
71 # config parameters.
72 #
73 cache = L1Cache(size = options.l1d_size,
74 assoc = options.l1d_assoc,
75 start_index_bit = block_size_bits)
76
|
77 #
78 # Only one unified L1 cache exists. Can cache instructions and data.
79 #
80 l1_cntrl = L1Cache_Controller(version = i,
81 cacheMemory = cache,
82 send_evictions = send_evicts(options),
83 transitions_per_cycle = options.ports,
84 clk_domain=system.cpu[i].clk_domain,
85 ruby_system = ruby_system)
| |
86
| 77
|
87 cpu_seq = RubySequencer(version = i,
88 icache = cache,
89 dcache = cache,
90 clk_domain=system.cpu[i].clk_domain,
91 ruby_system = ruby_system)
| 78 # the ruby random tester reuses num_cpus to specify the
79 # number of cpu ports connected to the tester object, which
80 # is stored in system.cpu. because there is only ever one
81 # tester object, num_cpus is not necessarily equal to the
82 # size of system.cpu; therefore if len(system.cpu) == 1
83 # we use system.cpu[0] to set the clk_domain, thereby ensuring
84 # we don't index off the end of the cpu list.
85 if len(system.cpu) == 1:
86 clk_domain = system.cpu[0].clk_domain
87 else:
88 clk_domain = system.cpu[i].clk_domain
|
92
| 89
|
| 90 # Only one unified L1 cache exists. Can cache instructions and data.
91 l1_cntrl = L1Cache_Controller(version=i, cacheMemory=cache,
92 send_evictions=send_evicts(options),
93 transitions_per_cycle=options.ports,
94 clk_domain=clk_domain,
95 ruby_system=ruby_system)
96
97 cpu_seq = RubySequencer(version=i, icache=cache, dcache=cache,
98 clk_domain=clk_domain, ruby_system=ruby_system)
99
|
93 l1_cntrl.sequencer = cpu_seq
94 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
95
96 # Add controllers and sequencers to the appropriate lists
97 cpu_sequencers.append(cpu_seq)
98 l1_cntrl_nodes.append(l1_cntrl)
99
100 # Connect the L1 controllers and the network
101 l1_cntrl.mandatoryQueue = MessageBuffer()
102 l1_cntrl.requestFromCache = MessageBuffer(ordered = True)
103 l1_cntrl.requestFromCache.master = ruby_system.network.slave
104 l1_cntrl.responseFromCache = MessageBuffer(ordered = True)
105 l1_cntrl.responseFromCache.master = ruby_system.network.slave
106 l1_cntrl.forwardToCache = MessageBuffer(ordered = True)
107 l1_cntrl.forwardToCache.slave = ruby_system.network.master
108 l1_cntrl.responseToCache = MessageBuffer(ordered = True)
109 l1_cntrl.responseToCache.slave = ruby_system.network.master
110
111 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
112 assert(phys_mem_size % options.num_dirs == 0)
113 mem_module_size = phys_mem_size / options.num_dirs
114
115 # Run each of the ruby memory controllers at a ratio of the frequency of
116 # the ruby system.
117 # clk_divider value is a fix to pass regression.
118 ruby_system.memctrl_clk_domain = DerivedClockDomain(
119 clk_domain=ruby_system.clk_domain,
120 clk_divider=3)
121
122 for i in xrange(options.num_dirs):
123 dir_size = MemorySize('0B')
124 dir_size.value = mem_module_size
125 dir_cntrl = Directory_Controller(version = i,
126 directory = RubyDirectoryMemory(
127 version = i, size = dir_size),
128 transitions_per_cycle = options.ports,
129 ruby_system = ruby_system)
130
131 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
132 dir_cntrl_nodes.append(dir_cntrl)
133
134 # Connect the directory controllers and the network
135 dir_cntrl.requestToDir = MessageBuffer(ordered = True)
136 dir_cntrl.requestToDir.slave = ruby_system.network.master
137 dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
138 dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
139
140 dir_cntrl.responseFromDir = MessageBuffer()
141 dir_cntrl.responseFromDir.master = ruby_system.network.slave
142 dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
143 dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
144 dir_cntrl.forwardFromDir = MessageBuffer()
145 dir_cntrl.forwardFromDir.master = ruby_system.network.slave
146 dir_cntrl.responseFromMemory = MessageBuffer()
147
148
149 for i, dma_port in enumerate(dma_ports):
150 #
151 # Create the Ruby objects associated with the dma controller
152 #
153 dma_seq = DMASequencer(version = i,
154 ruby_system = ruby_system)
155
156 dma_cntrl = DMA_Controller(version = i,
157 dma_sequencer = dma_seq,
158 transitions_per_cycle = options.ports,
159 ruby_system = ruby_system)
160
161 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
162 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
163 dma_cntrl_nodes.append(dma_cntrl)
164
165 # Connect the directory controllers and the network
166 dma_cntrl.mandatoryQueue = MessageBuffer()
167 dma_cntrl.requestToDir = MessageBuffer()
168 dma_cntrl.requestToDir.master = ruby_system.network.slave
169 dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
170 dma_cntrl.responseFromDir.slave = ruby_system.network.master
171
172 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
173
174 # Create the io controller and the sequencer
175 if full_system:
176 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
177 ruby_system._io_port = io_seq
178 io_controller = DMA_Controller(version = len(dma_ports),
179 dma_sequencer = io_seq,
180 ruby_system = ruby_system)
181 ruby_system.io_controller = io_controller
182
183 # Connect the dma controller to the network
184 io_controller.mandatoryQueue = MessageBuffer()
185 io_controller.requestToDir = MessageBuffer()
186 io_controller.requestToDir.master = ruby_system.network.slave
187 io_controller.responseFromDir = MessageBuffer(ordered = True)
188 io_controller.responseFromDir.slave = ruby_system.network.master
189
190 all_cntrls = all_cntrls + [io_controller]
191
192 ruby_system.network.number_of_virtual_networks = 5
193 topology = create_topology(all_cntrls, options)
194 return (cpu_sequencers, dir_cntrl_nodes, topology)
| 100 l1_cntrl.sequencer = cpu_seq
101 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
102
103 # Add controllers and sequencers to the appropriate lists
104 cpu_sequencers.append(cpu_seq)
105 l1_cntrl_nodes.append(l1_cntrl)
106
107 # Connect the L1 controllers and the network
108 l1_cntrl.mandatoryQueue = MessageBuffer()
109 l1_cntrl.requestFromCache = MessageBuffer(ordered = True)
110 l1_cntrl.requestFromCache.master = ruby_system.network.slave
111 l1_cntrl.responseFromCache = MessageBuffer(ordered = True)
112 l1_cntrl.responseFromCache.master = ruby_system.network.slave
113 l1_cntrl.forwardToCache = MessageBuffer(ordered = True)
114 l1_cntrl.forwardToCache.slave = ruby_system.network.master
115 l1_cntrl.responseToCache = MessageBuffer(ordered = True)
116 l1_cntrl.responseToCache.slave = ruby_system.network.master
117
118 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
119 assert(phys_mem_size % options.num_dirs == 0)
120 mem_module_size = phys_mem_size / options.num_dirs
121
122 # Run each of the ruby memory controllers at a ratio of the frequency of
123 # the ruby system.
124 # clk_divider value is a fix to pass regression.
125 ruby_system.memctrl_clk_domain = DerivedClockDomain(
126 clk_domain=ruby_system.clk_domain,
127 clk_divider=3)
128
129 for i in xrange(options.num_dirs):
130 dir_size = MemorySize('0B')
131 dir_size.value = mem_module_size
132 dir_cntrl = Directory_Controller(version = i,
133 directory = RubyDirectoryMemory(
134 version = i, size = dir_size),
135 transitions_per_cycle = options.ports,
136 ruby_system = ruby_system)
137
138 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
139 dir_cntrl_nodes.append(dir_cntrl)
140
141 # Connect the directory controllers and the network
142 dir_cntrl.requestToDir = MessageBuffer(ordered = True)
143 dir_cntrl.requestToDir.slave = ruby_system.network.master
144 dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
145 dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
146
147 dir_cntrl.responseFromDir = MessageBuffer()
148 dir_cntrl.responseFromDir.master = ruby_system.network.slave
149 dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
150 dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
151 dir_cntrl.forwardFromDir = MessageBuffer()
152 dir_cntrl.forwardFromDir.master = ruby_system.network.slave
153 dir_cntrl.responseFromMemory = MessageBuffer()
154
155
156 for i, dma_port in enumerate(dma_ports):
157 #
158 # Create the Ruby objects associated with the dma controller
159 #
160 dma_seq = DMASequencer(version = i,
161 ruby_system = ruby_system)
162
163 dma_cntrl = DMA_Controller(version = i,
164 dma_sequencer = dma_seq,
165 transitions_per_cycle = options.ports,
166 ruby_system = ruby_system)
167
168 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
169 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
170 dma_cntrl_nodes.append(dma_cntrl)
171
172 # Connect the directory controllers and the network
173 dma_cntrl.mandatoryQueue = MessageBuffer()
174 dma_cntrl.requestToDir = MessageBuffer()
175 dma_cntrl.requestToDir.master = ruby_system.network.slave
176 dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
177 dma_cntrl.responseFromDir.slave = ruby_system.network.master
178
179 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
180
181 # Create the io controller and the sequencer
182 if full_system:
183 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
184 ruby_system._io_port = io_seq
185 io_controller = DMA_Controller(version = len(dma_ports),
186 dma_sequencer = io_seq,
187 ruby_system = ruby_system)
188 ruby_system.io_controller = io_controller
189
190 # Connect the dma controller to the network
191 io_controller.mandatoryQueue = MessageBuffer()
192 io_controller.requestToDir = MessageBuffer()
193 io_controller.requestToDir.master = ruby_system.network.slave
194 io_controller.responseFromDir = MessageBuffer(ordered = True)
195 io_controller.responseFromDir.slave = ruby_system.network.master
196
197 all_cntrls = all_cntrls + [io_controller]
198
199 ruby_system.network.number_of_virtual_networks = 5
200 topology = create_topology(all_cntrls, options)
201 return (cpu_sequencers, dir_cntrl_nodes, topology)
|