1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the cache latency is only used by the sequencer on fast path hits
38#
39class Cache(RubyCache):
40 latency = 3
41
42def define_options(parser):
43 return
44
45def create_system(options, system, dma_ports, ruby_system):
46
47 if buildEnv['PROTOCOL'] != 'MI_example':
48 panic("This script requires the MI_example protocol to be built.")
49
50 cpu_sequencers = []
51
52 #
53 # The ruby network creation expects the list of nodes in the system to be
54 # consistent with the NetDest list. Therefore the l1 controller nodes must be
55 # listed before the directory nodes and directory nodes before dma nodes, etc.
56 #
57 l1_cntrl_nodes = []
58 dir_cntrl_nodes = []
59 dma_cntrl_nodes = []
60
61 #
62 # Must create the individual controllers before the network to ensure the
63 # controller constructors are called before the network constructor
64 #
65 block_size_bits = int(math.log(options.cacheline_size, 2))
66
67 for i in xrange(options.num_cpus):
68 #
69 # First create the Ruby objects associated with this cpu
70 # Only one cache exists for this protocol, so by default use the L1D
71 # config parameters.
72 #
73 cache = Cache(size = options.l1d_size,
74 assoc = options.l1d_assoc,
75 start_index_bit = block_size_bits)
76
77 #
78 # Only one unified L1 cache exists. Can cache instructions and data.
79 #
80 l1_cntrl = L1Cache_Controller(version = i,
81 cacheMemory = cache,
82 send_evictions = (
83 options.cpu_type == "detailed"),
84 transitions_per_cycle = options.ports,
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the cache latency is only used by the sequencer on fast path hits
38#
39class Cache(RubyCache):
40 latency = 3
41
42def define_options(parser):
43 return
44
45def create_system(options, system, dma_ports, ruby_system):
46
47 if buildEnv['PROTOCOL'] != 'MI_example':
48 panic("This script requires the MI_example protocol to be built.")
49
50 cpu_sequencers = []
51
52 #
53 # The ruby network creation expects the list of nodes in the system to be
54 # consistent with the NetDest list. Therefore the l1 controller nodes must be
55 # listed before the directory nodes and directory nodes before dma nodes, etc.
56 #
57 l1_cntrl_nodes = []
58 dir_cntrl_nodes = []
59 dma_cntrl_nodes = []
60
61 #
62 # Must create the individual controllers before the network to ensure the
63 # controller constructors are called before the network constructor
64 #
65 block_size_bits = int(math.log(options.cacheline_size, 2))
66
67 for i in xrange(options.num_cpus):
68 #
69 # First create the Ruby objects associated with this cpu
70 # Only one cache exists for this protocol, so by default use the L1D
71 # config parameters.
72 #
73 cache = Cache(size = options.l1d_size,
74 assoc = options.l1d_assoc,
75 start_index_bit = block_size_bits)
76
77 #
78 # Only one unified L1 cache exists. Can cache instructions and data.
79 #
80 l1_cntrl = L1Cache_Controller(version = i,
81 cacheMemory = cache,
82 send_evictions = (
83 options.cpu_type == "detailed"),
84 transitions_per_cycle = options.ports,
|
90 ruby_system = ruby_system)
91
92 l1_cntrl.sequencer = cpu_seq
93 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
94
95 #
96 # Add controllers and sequencers to the appropriate lists
97 #
98 cpu_sequencers.append(cpu_seq)
99 l1_cntrl_nodes.append(l1_cntrl)
100
101 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
102 assert(phys_mem_size % options.num_dirs == 0)
103 mem_module_size = phys_mem_size / options.num_dirs
104
105 # Run each of the ruby memory controllers at a ratio of the frequency of
106 # the ruby system.
107 # clk_divider value is a fix to pass regression.
108 ruby_system.memctrl_clk_domain = DerivedClockDomain(
109 clk_domain=ruby_system.clk_domain,
110 clk_divider=3)
111
112 for i in xrange(options.num_dirs):
113 #
114 # Create the Ruby objects associated with the directory controller
115 #
116
117 mem_cntrl = RubyMemoryControl(
118 clk_domain = ruby_system.memctrl_clk_domain,
119 version = i,
120 ruby_system = ruby_system)
121
122 dir_size = MemorySize('0B')
123 dir_size.value = mem_module_size
124
125 dir_cntrl = Directory_Controller(version = i,
126 directory = \
127 RubyDirectoryMemory( \
128 version = i,
129 size = dir_size,
130 use_map = options.use_map,
131 map_levels = \
132 options.map_levels),
133 memBuffer = mem_cntrl,
134 transitions_per_cycle = options.ports,
135 ruby_system = ruby_system)
136
137 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
138 dir_cntrl_nodes.append(dir_cntrl)
139
140 for i, dma_port in enumerate(dma_ports):
141 #
142 # Create the Ruby objects associated with the dma controller
143 #
144 dma_seq = DMASequencer(version = i,
145 ruby_system = ruby_system)
146
147 dma_cntrl = DMA_Controller(version = i,
148 dma_sequencer = dma_seq,
149 transitions_per_cycle = options.ports,
150 ruby_system = ruby_system)
151
152 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
153 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
154 dma_cntrl_nodes.append(dma_cntrl)
155
156 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
157
158 topology = create_topology(all_cntrls, options)
159
160 return (cpu_sequencers, dir_cntrl_nodes, topology)
| 92 ruby_system = ruby_system)
93
94 l1_cntrl.sequencer = cpu_seq
95 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
96
97 #
98 # Add controllers and sequencers to the appropriate lists
99 #
100 cpu_sequencers.append(cpu_seq)
101 l1_cntrl_nodes.append(l1_cntrl)
102
103 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
104 assert(phys_mem_size % options.num_dirs == 0)
105 mem_module_size = phys_mem_size / options.num_dirs
106
107 # Run each of the ruby memory controllers at a ratio of the frequency of
108 # the ruby system.
109 # clk_divider value is a fix to pass regression.
110 ruby_system.memctrl_clk_domain = DerivedClockDomain(
111 clk_domain=ruby_system.clk_domain,
112 clk_divider=3)
113
114 for i in xrange(options.num_dirs):
115 #
116 # Create the Ruby objects associated with the directory controller
117 #
118
119 mem_cntrl = RubyMemoryControl(
120 clk_domain = ruby_system.memctrl_clk_domain,
121 version = i,
122 ruby_system = ruby_system)
123
124 dir_size = MemorySize('0B')
125 dir_size.value = mem_module_size
126
127 dir_cntrl = Directory_Controller(version = i,
128 directory = \
129 RubyDirectoryMemory( \
130 version = i,
131 size = dir_size,
132 use_map = options.use_map,
133 map_levels = \
134 options.map_levels),
135 memBuffer = mem_cntrl,
136 transitions_per_cycle = options.ports,
137 ruby_system = ruby_system)
138
139 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
140 dir_cntrl_nodes.append(dir_cntrl)
141
142 for i, dma_port in enumerate(dma_ports):
143 #
144 # Create the Ruby objects associated with the dma controller
145 #
146 dma_seq = DMASequencer(version = i,
147 ruby_system = ruby_system)
148
149 dma_cntrl = DMA_Controller(version = i,
150 dma_sequencer = dma_seq,
151 transitions_per_cycle = options.ports,
152 ruby_system = ruby_system)
153
154 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
155 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
156 dma_cntrl_nodes.append(dma_cntrl)
157
158 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
159
160 topology = create_topology(all_cntrls, options)
161
162 return (cpu_sequencers, dir_cntrl_nodes, topology)
|