1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology 35 36# 37# Note: the cache latency is only used by the sequencer on fast path hits 38# 39class Cache(RubyCache): 40 latency = 3 41 42def define_options(parser): 43 return 44 45def create_system(options, system, piobus, dma_ports, ruby_system): 46 47 if buildEnv['PROTOCOL'] != 'MI_example': 48 panic("This script requires the MI_example protocol to be built.") 49 50 cpu_sequencers = [] 51 52 # 53 # The ruby network creation expects the list of nodes in the system to be 54 # consistent with the NetDest list. Therefore the l1 controller nodes must be 55 # listed before the directory nodes and directory nodes before dma nodes, etc. 56 # 57 l1_cntrl_nodes = [] 58 dir_cntrl_nodes = [] 59 dma_cntrl_nodes = [] 60 61 # 62 # Must create the individual controllers before the network to ensure the 63 # controller constructors are called before the network constructor 64 # 65 block_size_bits = int(math.log(options.cacheline_size, 2)) 66 67 for i in xrange(options.num_cpus): 68 # 69 # First create the Ruby objects associated with this cpu 70 # Only one cache exists for this protocol, so by default use the L1D 71 # config parameters. 72 # 73 cache = Cache(size = options.l1d_size, 74 assoc = options.l1d_assoc, 75 start_index_bit = block_size_bits) 76 77 # 78 # Only one unified L1 cache exists. Can cache instructions and data. 79 # 80 l1_cntrl = L1Cache_Controller(version = i, 81 cacheMemory = cache, 82 send_evictions = ( 83 options.cpu_type == "detailed"), 84 transitions_per_cycle = options.ports, 85 ruby_system = ruby_system) 86 87 cpu_seq = RubySequencer(version = i, 88 icache = cache, 89 dcache = cache, 90 ruby_system = ruby_system) 91 92 l1_cntrl.sequencer = cpu_seq 93 94 if piobus != None:
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology 35 36# 37# Note: the cache latency is only used by the sequencer on fast path hits 38# 39class Cache(RubyCache): 40 latency = 3 41 42def define_options(parser): 43 return 44 45def create_system(options, system, piobus, dma_ports, ruby_system): 46 47 if buildEnv['PROTOCOL'] != 'MI_example': 48 panic("This script requires the MI_example protocol to be built.") 49 50 cpu_sequencers = [] 51 52 # 53 # The ruby network creation expects the list of nodes in the system to be 54 # consistent with the NetDest list. Therefore the l1 controller nodes must be 55 # listed before the directory nodes and directory nodes before dma nodes, etc. 56 # 57 l1_cntrl_nodes = [] 58 dir_cntrl_nodes = [] 59 dma_cntrl_nodes = [] 60 61 # 62 # Must create the individual controllers before the network to ensure the 63 # controller constructors are called before the network constructor 64 # 65 block_size_bits = int(math.log(options.cacheline_size, 2)) 66 67 for i in xrange(options.num_cpus): 68 # 69 # First create the Ruby objects associated with this cpu 70 # Only one cache exists for this protocol, so by default use the L1D 71 # config parameters. 72 # 73 cache = Cache(size = options.l1d_size, 74 assoc = options.l1d_assoc, 75 start_index_bit = block_size_bits) 76 77 # 78 # Only one unified L1 cache exists. Can cache instructions and data. 79 # 80 l1_cntrl = L1Cache_Controller(version = i, 81 cacheMemory = cache, 82 send_evictions = ( 83 options.cpu_type == "detailed"), 84 transitions_per_cycle = options.ports, 85 ruby_system = ruby_system) 86 87 cpu_seq = RubySequencer(version = i, 88 icache = cache, 89 dcache = cache, 90 ruby_system = ruby_system) 91 92 l1_cntrl.sequencer = cpu_seq 93 94 if piobus != None:
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96 97 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 98 # 99 # Add controllers and sequencers to the appropriate lists 100 # 101 cpu_sequencers.append(cpu_seq) 102 l1_cntrl_nodes.append(l1_cntrl) 103 104 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 105 assert(phys_mem_size % options.num_dirs == 0) 106 mem_module_size = phys_mem_size / options.num_dirs 107 108 # Run each of the ruby memory controllers at a ratio of the frequency of 109 # the ruby system. 110 # clk_divider value is a fix to pass regression. 111 ruby_system.memctrl_clk_domain = DerivedClockDomain( 112 clk_domain=ruby_system.clk_domain, 113 clk_divider=3) 114 115 for i in xrange(options.num_dirs): 116 # 117 # Create the Ruby objects associated with the directory controller 118 # 119 120 mem_cntrl = RubyMemoryControl( 121 clk_domain = ruby_system.memctrl_clk_domain, 122 version = i, 123 ruby_system = ruby_system) 124 125 dir_size = MemorySize('0B') 126 dir_size.value = mem_module_size 127 128 dir_cntrl = Directory_Controller(version = i, 129 directory = \ 130 RubyDirectoryMemory( \ 131 version = i, 132 size = dir_size, 133 use_map = options.use_map, 134 map_levels = \ 135 options.map_levels), 136 memBuffer = mem_cntrl, 137 transitions_per_cycle = options.ports, 138 ruby_system = ruby_system) 139 140 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 141 dir_cntrl_nodes.append(dir_cntrl) 142 143 for i, dma_port in enumerate(dma_ports): 144 # 145 # Create the Ruby objects associated with the dma controller 146 # 147 dma_seq = DMASequencer(version = i, 148 ruby_system = ruby_system) 149 150 dma_cntrl = DMA_Controller(version = i, 151 dma_sequencer = dma_seq, 152 transitions_per_cycle = options.ports, 153 ruby_system = ruby_system) 154 155 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 156 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 157 dma_cntrl_nodes.append(dma_cntrl) 158 159 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 160 161 topology = create_topology(all_cntrls, options) 162 163 return (cpu_sequencers, dir_cntrl_nodes, topology)
| 98 99 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 100 # 101 # Add controllers and sequencers to the appropriate lists 102 # 103 cpu_sequencers.append(cpu_seq) 104 l1_cntrl_nodes.append(l1_cntrl) 105 106 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 107 assert(phys_mem_size % options.num_dirs == 0) 108 mem_module_size = phys_mem_size / options.num_dirs 109 110 # Run each of the ruby memory controllers at a ratio of the frequency of 111 # the ruby system. 112 # clk_divider value is a fix to pass regression. 113 ruby_system.memctrl_clk_domain = DerivedClockDomain( 114 clk_domain=ruby_system.clk_domain, 115 clk_divider=3) 116 117 for i in xrange(options.num_dirs): 118 # 119 # Create the Ruby objects associated with the directory controller 120 # 121 122 mem_cntrl = RubyMemoryControl( 123 clk_domain = ruby_system.memctrl_clk_domain, 124 version = i, 125 ruby_system = ruby_system) 126 127 dir_size = MemorySize('0B') 128 dir_size.value = mem_module_size 129 130 dir_cntrl = Directory_Controller(version = i, 131 directory = \ 132 RubyDirectoryMemory( \ 133 version = i, 134 size = dir_size, 135 use_map = options.use_map, 136 map_levels = \ 137 options.map_levels), 138 memBuffer = mem_cntrl, 139 transitions_per_cycle = options.ports, 140 ruby_system = ruby_system) 141 142 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 143 dir_cntrl_nodes.append(dir_cntrl) 144 145 for i, dma_port in enumerate(dma_ports): 146 # 147 # Create the Ruby objects associated with the dma controller 148 # 149 dma_seq = DMASequencer(version = i, 150 ruby_system = ruby_system) 151 152 dma_cntrl = DMA_Controller(version = i, 153 dma_sequencer = dma_seq, 154 transitions_per_cycle = options.ports, 155 ruby_system = ruby_system) 156 157 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 158 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 159 dma_cntrl_nodes.append(dma_cntrl) 160 161 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 162 163 topology = create_topology(all_cntrls, options) 164 165 return (cpu_sequencers, dir_cntrl_nodes, topology)
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