MI_example.py (8717:5c253f1031d7) | MI_example.py (8845:a230379caf65) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 81 unchanged lines hidden (view full) --- 90 dcache = cache, 91 physMemPort = system.physmem.port, 92 physmem = system.physmem, 93 ruby_system = ruby_system) 94 95 l1_cntrl.sequencer = cpu_seq 96 97 if piobus != None: | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 81 unchanged lines hidden (view full) --- 90 dcache = cache, 91 physMemPort = system.physmem.port, 92 physmem = system.physmem, 93 ruby_system = ruby_system) 94 95 l1_cntrl.sequencer = cpu_seq 96 97 if piobus != None: |
98 cpu_seq.pio_port = piobus.port | 98 cpu_seq.pio_port = piobus.slave |
99 100 exec("system.l1_cntrl%d = l1_cntrl" % i) 101 # 102 # Add controllers and sequencers to the appropriate lists 103 # 104 cpu_sequencers.append(cpu_seq) 105 l1_cntrl_nodes.append(l1_cntrl) 106 --- 41 unchanged lines hidden (view full) --- 148 149 dma_cntrl = DMA_Controller(version = i, 150 cntrl_id = cntrl_count, 151 dma_sequencer = dma_seq, 152 ruby_system = ruby_system) 153 154 exec("system.dma_cntrl%d = dma_cntrl" % i) 155 if dma_device.type == 'MemTest': | 99 100 exec("system.l1_cntrl%d = l1_cntrl" % i) 101 # 102 # Add controllers and sequencers to the appropriate lists 103 # 104 cpu_sequencers.append(cpu_seq) 105 l1_cntrl_nodes.append(l1_cntrl) 106 --- 41 unchanged lines hidden (view full) --- 148 149 dma_cntrl = DMA_Controller(version = i, 150 cntrl_id = cntrl_count, 151 dma_sequencer = dma_seq, 152 ruby_system = ruby_system) 153 154 exec("system.dma_cntrl%d = dma_cntrl" % i) 155 if dma_device.type == 'MemTest': |
156 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) | 156 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i) |
157 else: | 157 else: |
158 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 159 dma_cntrl.dma_sequencer.port = dma_device.dma | 158 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i) 159 dma_cntrl.dma_sequencer.slave = dma_device.dma |
160 dma_cntrl_nodes.append(dma_cntrl) 161 162 cntrl_count += 1 163 164 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 165 166 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) | 160 dma_cntrl_nodes.append(dma_cntrl) 161 162 cntrl_count += 1 163 164 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 165 166 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) |