MI_example.py (11019:fc1e41e88fd3) | MI_example.py (11022:e6e3b7097810) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 84 unchanged lines hidden (view full) --- 93 l1_cntrl.sequencer = cpu_seq 94 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 95 96 # Add controllers and sequencers to the appropriate lists 97 cpu_sequencers.append(cpu_seq) 98 l1_cntrl_nodes.append(l1_cntrl) 99 100 # Connect the L1 controllers and the network | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 84 unchanged lines hidden (view full) --- 93 l1_cntrl.sequencer = cpu_seq 94 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 95 96 # Add controllers and sequencers to the appropriate lists 97 cpu_sequencers.append(cpu_seq) 98 l1_cntrl_nodes.append(l1_cntrl) 99 100 # Connect the L1 controllers and the network |
101 l1_cntrl.requestFromCache = ruby_system.network.slave 102 l1_cntrl.responseFromCache = ruby_system.network.slave 103 l1_cntrl.forwardToCache = ruby_system.network.master 104 l1_cntrl.responseToCache = ruby_system.network.master | 101 l1_cntrl.mandatoryQueue = MessageBuffer() 102 l1_cntrl.requestFromCache = MessageBuffer(ordered = True) 103 l1_cntrl.requestFromCache.master = ruby_system.network.slave 104 l1_cntrl.responseFromCache = MessageBuffer(ordered = True) 105 l1_cntrl.responseFromCache.master = ruby_system.network.slave 106 l1_cntrl.forwardToCache = MessageBuffer(ordered = True) 107 l1_cntrl.forwardToCache.slave = ruby_system.network.master 108 l1_cntrl.responseToCache = MessageBuffer(ordered = True) 109 l1_cntrl.responseToCache.slave = ruby_system.network.master |
105 | 110 |
106 | |
107 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 108 assert(phys_mem_size % options.num_dirs == 0) 109 mem_module_size = phys_mem_size / options.num_dirs 110 111 # Run each of the ruby memory controllers at a ratio of the frequency of 112 # the ruby system. 113 # clk_divider value is a fix to pass regression. 114 ruby_system.memctrl_clk_domain = DerivedClockDomain( --- 8 unchanged lines hidden (view full) --- 123 version = i, size = dir_size), 124 transitions_per_cycle = options.ports, 125 ruby_system = ruby_system) 126 127 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 128 dir_cntrl_nodes.append(dir_cntrl) 129 130 # Connect the directory controllers and the network | 111 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 112 assert(phys_mem_size % options.num_dirs == 0) 113 mem_module_size = phys_mem_size / options.num_dirs 114 115 # Run each of the ruby memory controllers at a ratio of the frequency of 116 # the ruby system. 117 # clk_divider value is a fix to pass regression. 118 ruby_system.memctrl_clk_domain = DerivedClockDomain( --- 8 unchanged lines hidden (view full) --- 127 version = i, size = dir_size), 128 transitions_per_cycle = options.ports, 129 ruby_system = ruby_system) 130 131 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 132 dir_cntrl_nodes.append(dir_cntrl) 133 134 # Connect the directory controllers and the network |
131 dir_cntrl.requestToDir = ruby_system.network.master 132 dir_cntrl.dmaRequestToDir = ruby_system.network.master | 135 dir_cntrl.requestToDir = MessageBuffer(ordered = True) 136 dir_cntrl.requestToDir.slave = ruby_system.network.master 137 dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True) 138 dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master |
133 | 139 |
134 dir_cntrl.responseFromDir = ruby_system.network.slave 135 dir_cntrl.dmaResponseFromDir = ruby_system.network.slave 136 dir_cntrl.forwardFromDir = ruby_system.network.slave | 140 dir_cntrl.responseFromDir = MessageBuffer() 141 dir_cntrl.responseFromDir.master = ruby_system.network.slave 142 dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True) 143 dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave 144 dir_cntrl.forwardFromDir = MessageBuffer() 145 dir_cntrl.forwardFromDir.master = ruby_system.network.slave 146 dir_cntrl.responseFromMemory = MessageBuffer() |
137 138 139 for i, dma_port in enumerate(dma_ports): 140 # 141 # Create the Ruby objects associated with the dma controller 142 # 143 dma_seq = DMASequencer(version = i, 144 ruby_system = ruby_system) 145 146 dma_cntrl = DMA_Controller(version = i, 147 dma_sequencer = dma_seq, 148 transitions_per_cycle = options.ports, 149 ruby_system = ruby_system) 150 151 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 152 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 153 dma_cntrl_nodes.append(dma_cntrl) 154 155 # Connect the directory controllers and the network | 147 148 149 for i, dma_port in enumerate(dma_ports): 150 # 151 # Create the Ruby objects associated with the dma controller 152 # 153 dma_seq = DMASequencer(version = i, 154 ruby_system = ruby_system) 155 156 dma_cntrl = DMA_Controller(version = i, 157 dma_sequencer = dma_seq, 158 transitions_per_cycle = options.ports, 159 ruby_system = ruby_system) 160 161 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 162 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 163 dma_cntrl_nodes.append(dma_cntrl) 164 165 # Connect the directory controllers and the network |
156 dma_cntrl.requestToDir = ruby_system.network.slave 157 dma_cntrl.responseFromDir = ruby_system.network.master | 166 dma_cntrl.mandatoryQueue = MessageBuffer() 167 dma_cntrl.requestToDir = MessageBuffer() 168 dma_cntrl.requestToDir.master = ruby_system.network.slave 169 dma_cntrl.responseFromDir = MessageBuffer(ordered = True) 170 dma_cntrl.responseFromDir.slave = ruby_system.network.master |
158 159 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 160 161 # Create the io controller and the sequencer 162 if full_system: 163 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 164 ruby_system._io_port = io_seq 165 io_controller = DMA_Controller(version = len(dma_ports), 166 dma_sequencer = io_seq, 167 ruby_system = ruby_system) 168 ruby_system.io_controller = io_controller 169 170 # Connect the dma controller to the network | 171 172 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 173 174 # Create the io controller and the sequencer 175 if full_system: 176 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 177 ruby_system._io_port = io_seq 178 io_controller = DMA_Controller(version = len(dma_ports), 179 dma_sequencer = io_seq, 180 ruby_system = ruby_system) 181 ruby_system.io_controller = io_controller 182 183 # Connect the dma controller to the network |
171 io_controller.responseFromDir = ruby_system.network.master 172 io_controller.requestToDir = ruby_system.network.slave | 184 io_controller.mandatoryQueue = MessageBuffer() 185 io_controller.requestToDir = MessageBuffer() 186 io_controller.requestToDir.master = ruby_system.network.slave 187 io_controller.responseFromDir = MessageBuffer(ordered = True) 188 io_controller.responseFromDir.slave = ruby_system.network.master |
173 174 all_cntrls = all_cntrls + [io_controller] 175 176 topology = create_topology(all_cntrls, options) 177 return (cpu_sequencers, dir_cntrl_nodes, topology) | 189 190 all_cntrls = all_cntrls + [io_controller] 191 192 topology = create_topology(all_cntrls, options) 193 return (cpu_sequencers, dir_cntrl_nodes, topology) |