1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 17 unchanged lines hidden (view full) ---

26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34
35#
36# Note: the cache latency is only used by the sequencer on fast path hits
37#
38class Cache(RubyCache):
39 latency = 3
40
41def define_options(parser):

--- 108 unchanged lines hidden (view full) ---

150
151 exec("system.dma_cntrl%d = dma_cntrl" % i)
152 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
153 dma_cntrl_nodes.append(dma_cntrl)
154 cntrl_count += 1
155
156 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
157
158 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)