1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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57 dir_cntrl_nodes = []
58 dma_cntrl_nodes = []
59
60 #
61 # Must create the individual controllers before the network to ensure the
62 # controller constructors are called before the network constructor
63 #
64 block_size_bits = int(math.log(options.cacheline_size, 2))
65
66 for i in xrange(options.num_cpus):
67 #
68 # First create the Ruby objects associated with this cpu
69 # Only one cache exists for this protocol, so by default use the L1D
70 # config parameters.
71 #
72 cache = Cache(size = options.l1d_size,

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81 dcache = cache,
82 physMemPort = system.physmem.port,
83 physmem = system.physmem)
84
85 if piobus != None:
86 cpu_seq.pio_port = piobus.port
87
88 l1_cntrl = L1Cache_Controller(version = i,
89 sequencer = cpu_seq,
90 cacheMemory = cache)
91
92 exec("system.l1_cntrl%d = l1_cntrl" % i)
93 #
94 # Add controllers and sequencers to the appropriate lists
95 #
96 cpu_sequencers.append(cpu_seq)
97 l1_cntrl_nodes.append(l1_cntrl)
98
99 phys_mem_size = long(system.physmem.range.second) - \
100 long(system.physmem.range.first) + 1
101 mem_module_size = phys_mem_size / options.num_dirs
102
103 for i in xrange(options.num_dirs):
104 #
105 # Create the Ruby objects associated with the directory controller
106 #
107
108 mem_cntrl = RubyMemoryControl(version = i)
109
110 dir_size = MemorySize('0B')
111 dir_size.value = mem_module_size
112
113 dir_cntrl = Directory_Controller(version = i,
114 directory = \
115 RubyDirectoryMemory( \
116 version = i,
117 size = dir_size,
118 use_map = options.use_map,
119 map_levels = \
120 options.map_levels),
121 memBuffer = mem_cntrl)
122
123 exec("system.dir_cntrl%d = dir_cntrl" % i)
124 dir_cntrl_nodes.append(dir_cntrl)
125
126 for i, dma_device in enumerate(dma_devices):
127 #
128 # Create the Ruby objects associated with the dma controller
129 #
130 dma_seq = DMASequencer(version = i,
131 physMemPort = system.physmem.port,
132 physmem = system.physmem)
133
134 dma_cntrl = DMA_Controller(version = i,
135 dma_sequencer = dma_seq)
136
137 exec("system.dma_cntrl%d = dma_cntrl" % i)
138 if dma_device.type == 'MemTest':
139 system.dma_cntrl.dma_sequencer.port = dma_device.test
140 else:
141 system.dma_cntrl.dma_sequencer.port = dma_device.dma
142 dma_cntrl.dma_sequencer.port = dma_device.dma
143 dma_cntrl_nodes.append(dma_cntrl)
144
145 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
146
147 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)