1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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37#
38# Declare caches used by the protocol
39#
40class L1Cache(RubyCache): pass
41
42def define_options(parser):
43 return
44
45def create_system(options, full_system, system, dma_ports, ruby_system):
46
47 if buildEnv['PROTOCOL'] != 'MI_example':
48 panic("This script requires the MI_example protocol to be built.")
49
50 cpu_sequencers = []
51
52 #
53 # The ruby network creation expects the list of nodes in the system to be

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120
121 # Run each of the ruby memory controllers at a ratio of the frequency of
122 # the ruby system.
123 # clk_divider value is a fix to pass regression.
124 ruby_system.memctrl_clk_domain = DerivedClockDomain(
125 clk_domain=ruby_system.clk_domain,
126 clk_divider=3)
127
128 dir_cntrl_nodes = create_directories(options, system.mem_ranges,
129 ruby_system)
130 for dir_cntrl in dir_cntrl_nodes:
131 # Connect the directory controllers and the network
132 dir_cntrl.requestToDir = MessageBuffer(ordered = True)
133 dir_cntrl.requestToDir.slave = ruby_system.network.master
134 dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
135 dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
136
137 dir_cntrl.responseFromDir = MessageBuffer()

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183 io_controller.requestToDir.master = ruby_system.network.slave
184 io_controller.responseFromDir = MessageBuffer(ordered = True)
185 io_controller.responseFromDir.slave = ruby_system.network.master
186
187 all_cntrls = all_cntrls + [io_controller]
188
189 ruby_system.network.number_of_virtual_networks = 5
190 topology = create_topology(all_cntrls, options)
191 return (cpu_sequencers, dir_cntrl_nodes, topology)