1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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69 # First create the Ruby objects associated with this cpu
70 # Only one cache exists for this protocol, so by default use the L1D
71 # config parameters.
72 #
73 cache = L1Cache(size = options.l1d_size,
74 assoc = options.l1d_assoc,
75 start_index_bit = block_size_bits)
76
77 #
78 # Only one unified L1 cache exists. Can cache instructions and data.
79 #
80 l1_cntrl = L1Cache_Controller(version = i,
81 cacheMemory = cache,
82 send_evictions = send_evicts(options),
83 transitions_per_cycle = options.ports,
84 clk_domain=system.cpu[i].clk_domain,
85 ruby_system = ruby_system)
86
87 cpu_seq = RubySequencer(version = i,
88 icache = cache,
89 dcache = cache,
90 clk_domain=system.cpu[i].clk_domain,
91 ruby_system = ruby_system)
92
93 l1_cntrl.sequencer = cpu_seq
94 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
95
96 # Add controllers and sequencers to the appropriate lists
97 cpu_sequencers.append(cpu_seq)
98 l1_cntrl_nodes.append(l1_cntrl)
99
100 # Connect the L1 controllers and the network

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