1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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93 l1_cntrl.sequencer = cpu_seq
94 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
95
96 # Add controllers and sequencers to the appropriate lists
97 cpu_sequencers.append(cpu_seq)
98 l1_cntrl_nodes.append(l1_cntrl)
99
100 # Connect the L1 controllers and the network
101 l1_cntrl.requestFromCache = ruby_system.network.slave
102 l1_cntrl.responseFromCache = ruby_system.network.slave
103 l1_cntrl.forwardToCache = ruby_system.network.master
104 l1_cntrl.responseToCache = ruby_system.network.master
105
106
107 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
108 assert(phys_mem_size % options.num_dirs == 0)
109 mem_module_size = phys_mem_size / options.num_dirs
110
111 # Run each of the ruby memory controllers at a ratio of the frequency of
112 # the ruby system.
113 # clk_divider value is a fix to pass regression.
114 ruby_system.memctrl_clk_domain = DerivedClockDomain(

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123 version = i, size = dir_size),
124 transitions_per_cycle = options.ports,
125 ruby_system = ruby_system)
126
127 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
128 dir_cntrl_nodes.append(dir_cntrl)
129
130 # Connect the directory controllers and the network
131 dir_cntrl.requestToDir = ruby_system.network.master
132 dir_cntrl.dmaRequestToDir = ruby_system.network.master
133
134 dir_cntrl.responseFromDir = ruby_system.network.slave
135 dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
136 dir_cntrl.forwardFromDir = ruby_system.network.slave
137
138
139 for i, dma_port in enumerate(dma_ports):
140 #
141 # Create the Ruby objects associated with the dma controller
142 #
143 dma_seq = DMASequencer(version = i,
144 ruby_system = ruby_system)
145
146 dma_cntrl = DMA_Controller(version = i,
147 dma_sequencer = dma_seq,
148 transitions_per_cycle = options.ports,
149 ruby_system = ruby_system)
150
151 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
152 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
153 dma_cntrl_nodes.append(dma_cntrl)
154
155 # Connect the directory controllers and the network
156 dma_cntrl.requestToDir = ruby_system.network.slave
157 dma_cntrl.responseFromDir = ruby_system.network.master
158
159 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
160
161 # Create the io controller and the sequencer
162 if full_system:
163 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
164 ruby_system._io_port = io_seq
165 io_controller = DMA_Controller(version = len(dma_ports),
166 dma_sequencer = io_seq,
167 ruby_system = ruby_system)
168 ruby_system.io_controller = io_controller
169
170 # Connect the dma controller to the network
171 io_controller.responseFromDir = ruby_system.network.master
172 io_controller.requestToDir = ruby_system.network.slave
173
174 all_cntrls = all_cntrls + [io_controller]
175
176 topology = create_topology(all_cntrls, options)
177 return (cpu_sequencers, dir_cntrl_nodes, topology)