1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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89 icache = cache,
90 dcache = cache,
91 clk_domain=system.cpu[i].clk_domain,
92 ruby_system = ruby_system)
93
94 l1_cntrl.sequencer = cpu_seq
95 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
96
97 #
98 # Add controllers and sequencers to the appropriate lists
99 #
100 cpu_sequencers.append(cpu_seq)
101 l1_cntrl_nodes.append(l1_cntrl)
102
103 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
104 assert(phys_mem_size % options.num_dirs == 0)
105 mem_module_size = phys_mem_size / options.num_dirs
106
107 # Run each of the ruby memory controllers at a ratio of the frequency of
108 # the ruby system.
109 # clk_divider value is a fix to pass regression.
110 ruby_system.memctrl_clk_domain = DerivedClockDomain(

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134 options.map_levels),
135 memBuffer = mem_cntrl,
136 transitions_per_cycle = options.ports,
137 ruby_system = ruby_system)
138
139 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
140 dir_cntrl_nodes.append(dir_cntrl)
141
142 for i, dma_port in enumerate(dma_ports):
143 #
144 # Create the Ruby objects associated with the dma controller
145 #
146 dma_seq = DMASequencer(version = i,
147 ruby_system = ruby_system)
148
149 dma_cntrl = DMA_Controller(version = i,
150 dma_sequencer = dma_seq,
151 transitions_per_cycle = options.ports,
152 ruby_system = ruby_system)
153
154 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
155 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
156 dma_cntrl_nodes.append(dma_cntrl)
157
158 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
159
160 topology = create_topology(all_cntrls, options)
161
162 return (cpu_sequencers, dir_cntrl_nodes, topology)