1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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112 # Run each of the ruby memory controllers at a ratio of the frequency of
113 # the ruby system.
114 # clk_divider value is a fix to pass regression.
115 ruby_system.memctrl_clk_domain = DerivedClockDomain(
116 clk_domain=ruby_system.clk_domain,
117 clk_divider=3)
118
119 for i in xrange(options.num_dirs):
120 dir_size = MemorySize('0B')
121 dir_size.value = mem_module_size
122 dir_cntrl = Directory_Controller(version = i,
123 directory = RubyDirectoryMemory(
124 version = i, size = dir_size),
125 transitions_per_cycle = options.ports,
126 ruby_system = ruby_system)
127
128 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
129 dir_cntrl_nodes.append(dir_cntrl)
130
131 # Connect the directory controllers and the network
132 dir_cntrl.requestToDir = ruby_system.network.master

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