| MESI_Two_Level.py (12976:125099a94768) | MESI_Two_Level.py (13731:67cd980cb20f) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 53 unchanged lines hidden (view full) --- 62 63 # 64 # Must create the individual controllers before the network to ensure the 65 # controller constructors are called before the network constructor 66 # 67 l2_bits = int(math.log(options.num_l2caches, 2)) 68 block_size_bits = int(math.log(options.cacheline_size, 2)) 69 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 53 unchanged lines hidden (view full) --- 62 63 # 64 # Must create the individual controllers before the network to ensure the 65 # controller constructors are called before the network constructor 66 # 67 l2_bits = int(math.log(options.num_l2caches, 2)) 68 block_size_bits = int(math.log(options.cacheline_size, 2)) 69 |
| 70 for i in xrange(options.num_cpus): | 70 for i in range(options.num_cpus): |
| 71 # 72 # First create the Ruby objects associated with this cpu 73 # 74 l1i_cache = L1Cache(size = options.l1i_size, 75 assoc = options.l1i_assoc, 76 start_index_bit = block_size_bits, 77 is_icache = True) 78 l1d_cache = L1Cache(size = options.l1d_size, --- 51 unchanged lines hidden (view full) --- 130 l1_cntrl.requestToL1Cache = MessageBuffer() 131 l1_cntrl.requestToL1Cache.slave = ruby_system.network.master 132 l1_cntrl.responseToL1Cache = MessageBuffer() 133 l1_cntrl.responseToL1Cache.slave = ruby_system.network.master 134 135 136 l2_index_start = block_size_bits + l2_bits 137 | 71 # 72 # First create the Ruby objects associated with this cpu 73 # 74 l1i_cache = L1Cache(size = options.l1i_size, 75 assoc = options.l1i_assoc, 76 start_index_bit = block_size_bits, 77 is_icache = True) 78 l1d_cache = L1Cache(size = options.l1d_size, --- 51 unchanged lines hidden (view full) --- 130 l1_cntrl.requestToL1Cache = MessageBuffer() 131 l1_cntrl.requestToL1Cache.slave = ruby_system.network.master 132 l1_cntrl.responseToL1Cache = MessageBuffer() 133 l1_cntrl.responseToL1Cache.slave = ruby_system.network.master 134 135 136 l2_index_start = block_size_bits + l2_bits 137 |
| 138 for i in xrange(options.num_l2caches): | 138 for i in range(options.num_l2caches): |
| 139 # 140 # First create the Ruby objects associated with this cpu 141 # 142 l2_cache = L2Cache(size = options.l2_size, 143 assoc = options.l2_assoc, 144 start_index_bit = l2_index_start) 145 146 l2_cntrl = L2Cache_Controller(version = i, --- 92 unchanged lines hidden --- | 139 # 140 # First create the Ruby objects associated with this cpu 141 # 142 l2_cache = L2Cache(size = options.l2_size, 143 assoc = options.l2_assoc, 144 start_index_bit = l2_index_start) 145 146 l2_cntrl = L2Cache_Controller(version = i, --- 92 unchanged lines hidden --- |