MESI_Two_Level.py (10524:fff17530cef6) | MESI_Two_Level.py (10529:05b5a6cf3521) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology |
35from Ruby import send_evicts |
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35 36# 37# Note: the L1 Cache latency is only used by the sequencer on fast path hits 38# 39class L1Cache(RubyCache): 40 latency = 3 41 42# --- 43 unchanged lines hidden (view full) --- 86 is_icache = False) 87 88 prefetcher = RubyPrefetcher.Prefetcher() 89 90 l1_cntrl = L1Cache_Controller(version = i, 91 L1Icache = l1i_cache, 92 L1Dcache = l1d_cache, 93 l2_select_num_bits = l2_bits, | 36 37# 38# Note: the L1 Cache latency is only used by the sequencer on fast path hits 39# 40class L1Cache(RubyCache): 41 latency = 3 42 43# --- 43 unchanged lines hidden (view full) --- 87 is_icache = False) 88 89 prefetcher = RubyPrefetcher.Prefetcher() 90 91 l1_cntrl = L1Cache_Controller(version = i, 92 L1Icache = l1i_cache, 93 L1Dcache = l1d_cache, 94 l2_select_num_bits = l2_bits, |
94 send_evictions = ( 95 options.cpu_type == "detailed"), | 95 send_evictions = send_evicts(options), |
96 prefetcher = prefetcher, 97 ruby_system = ruby_system, 98 clk_domain=system.cpu[i].clk_domain, 99 transitions_per_cycle=options.ports, 100 enable_prefetch = False) 101 102 cpu_seq = RubySequencer(version = i, 103 icache = l1i_cache, --- 119 unchanged lines hidden --- | 96 prefetcher = prefetcher, 97 ruby_system = ruby_system, 98 clk_domain=system.cpu[i].clk_domain, 99 transitions_per_cycle=options.ports, 100 enable_prefetch = False) 101 102 cpu_seq = RubySequencer(version = i, 103 icache = l1i_cache, --- 119 unchanged lines hidden --- |