MESI_Two_Level.py (10090:4eec7bdde5b0) MESI_Two_Level.py (10116:d61a59beb670)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 15
47
48def define_options(parser):
49 return
50
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 34 unchanged lines hidden (view full) ---

43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 15
47
48def define_options(parser):
49 return
50
51def create_system(options, system, piobus, dma_ports, ruby_system):
51def create_system(options, system, dma_ports, ruby_system):
52
53 if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
54 fatal("This script requires the MESI_Two_Level protocol to be built.")
55
56 cpu_sequencers = []
57
58 #
59 # The ruby network creation expects the list of nodes in the system to be

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99 enable_prefetch = False)
100
101 cpu_seq = RubySequencer(version = i,
102 icache = l1i_cache,
103 dcache = l1d_cache,
104 ruby_system = ruby_system)
105
106 l1_cntrl.sequencer = cpu_seq
52
53 if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
54 fatal("This script requires the MESI_Two_Level protocol to be built.")
55
56 cpu_sequencers = []
57
58 #
59 # The ruby network creation expects the list of nodes in the system to be

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99 enable_prefetch = False)
100
101 cpu_seq = RubySequencer(version = i,
102 icache = l1i_cache,
103 dcache = l1d_cache,
104 ruby_system = ruby_system)
105
106 l1_cntrl.sequencer = cpu_seq
107
108 if piobus != None:
109 cpu_seq.pio_master_port = piobus.slave
110 cpu_seq.mem_master_port = piobus.slave
111 cpu_seq.pio_slave_port = piobus.master
112
113 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
114
115 #
116 # Add controllers and sequencers to the appropriate lists
117 #
118 cpu_sequencers.append(cpu_seq)
119 l1_cntrl_nodes.append(l1_cntrl)
120

--- 79 unchanged lines hidden --- 		107 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
108
109 #
110 # Add controllers and sequencers to the appropriate lists
111 #
112 cpu_sequencers.append(cpu_seq)
113 l1_cntrl_nodes.append(l1_cntrl)
114

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