MESI_Two_Level.py (10007:94d286db85c1) MESI_Two_Level.py (10090:4eec7bdde5b0)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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101 cpu_seq = RubySequencer(version = i,
102 icache = l1i_cache,
103 dcache = l1d_cache,
104 ruby_system = ruby_system)
105
106 l1_cntrl.sequencer = cpu_seq
107
108 if piobus != None:
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 92 unchanged lines hidden (view full) ---

101 cpu_seq = RubySequencer(version = i,
102 icache = l1i_cache,
103 dcache = l1d_cache,
104 ruby_system = ruby_system)
105
106 l1_cntrl.sequencer = cpu_seq
107
108 if piobus != None:
109 cpu_seq.pio_port = piobus.slave
109 cpu_seq.pio_master_port = piobus.slave
110 cpu_seq.mem_master_port = piobus.slave
111 cpu_seq.pio_slave_port = piobus.master
110
111 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
112
113 #
114 # Add controllers and sequencers to the appropriate lists
115 #
116 cpu_sequencers.append(cpu_seq)
117 l1_cntrl_nodes.append(l1_cntrl)

--- 80 unchanged lines hidden --- 		112
113 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
114
115 #
116 # Add controllers and sequencers to the appropriate lists
117 #
118 cpu_sequencers.append(cpu_seq)
119 l1_cntrl_nodes.append(l1_cntrl)

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