1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 161 unchanged lines hidden (view full) --- 170 # Run each of the ruby memory controllers at a ratio of the frequency of 171 # the ruby system 172 # clk_divider value is a fix to pass regression. 173 ruby_system.memctrl_clk_domain = DerivedClockDomain( 174 clk_domain = ruby_system.clk_domain, 175 clk_divider = 3) 176 177 mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( |
178 options, bootmem, ruby_system, system) |
179 dir_cntrl_nodes = mem_dir_cntrl_nodes[:] 180 if rom_dir_cntrl_node is not None: 181 dir_cntrl_nodes.append(rom_dir_cntrl_node) 182 for dir_cntrl in dir_cntrl_nodes: 183 # Connect the directory controllers and the network 184 dir_cntrl.requestToDir = MessageBuffer() 185 dir_cntrl.requestToDir.slave = ruby_system.network.master 186 dir_cntrl.responseToDir = MessageBuffer() --- 52 unchanged lines hidden --- |