1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 68 unchanged lines hidden (view full) --- 77 is_icache = True) 78 l1d_cache = L1Cache(size = options.l1d_size, 79 assoc = options.l1d_assoc, 80 start_index_bit = block_size_bits, 81 is_icache = False) 82 83 prefetcher = RubyPrefetcher.Prefetcher() 84 |
85 # the ruby random tester reuses num_cpus to specify the 86 # number of cpu ports connected to the tester object, which 87 # is stored in system.cpu. because there is only ever one 88 # tester object, num_cpus is not necessarily equal to the 89 # size of system.cpu; therefore if len(system.cpu) == 1 90 # we use system.cpu[0] to set the clk_domain, thereby ensuring 91 # we don't index off the end of the cpu list. 92 if len(system.cpu) == 1: 93 clk_domain = system.cpu[0].clk_domain 94 else: 95 clk_domain = system.cpu[i].clk_domain 96 97 l1_cntrl = L1Cache_Controller(version = i, L1Icache = l1i_cache, |
98 L1Dcache = l1d_cache, 99 l2_select_num_bits = l2_bits, 100 send_evictions = send_evicts(options), 101 prefetcher = prefetcher, 102 ruby_system = ruby_system, |
103 clk_domain = clk_domain, 104 transitions_per_cycle = options.ports, |
105 enable_prefetch = False) 106 |
107 cpu_seq = RubySequencer(version = i, icache = l1i_cache, 108 dcache = l1d_cache, clk_domain = clk_domain, |
109 ruby_system = ruby_system) 110 |
111 |
112 l1_cntrl.sequencer = cpu_seq 113 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 114 115 # Add controllers and sequencers to the appropriate lists 116 cpu_sequencers.append(cpu_seq) 117 l1_cntrl_nodes.append(l1_cntrl) 118 119 # Connect the L1 controllers and the network --- 20 unchanged lines hidden (view full) --- 140 # First create the Ruby objects associated with this cpu 141 # 142 l2_cache = L2Cache(size = options.l2_size, 143 assoc = options.l2_assoc, 144 start_index_bit = l2_index_start) 145 146 l2_cntrl = L2Cache_Controller(version = i, 147 L2cache = l2_cache, |
148 transitions_per_cycle = options.ports, |
149 ruby_system = ruby_system) 150 151 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 152 l2_cntrl_nodes.append(l2_cntrl) 153 154 # Connect the L2 controllers and the network 155 l2_cntrl.DirRequestFromL2Cache = MessageBuffer() 156 l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave --- 14 unchanged lines hidden (view full) --- 171 assert(phys_mem_size % options.num_dirs == 0) 172 mem_module_size = phys_mem_size / options.num_dirs 173 174 175 # Run each of the ruby memory controllers at a ratio of the frequency of 176 # the ruby system 177 # clk_divider value is a fix to pass regression. 178 ruby_system.memctrl_clk_domain = DerivedClockDomain( |
179 clk_domain = ruby_system.clk_domain, 180 clk_divider = 3) |
181 182 for i in xrange(options.num_dirs): 183 dir_size = MemorySize('0B') 184 dir_size.value = mem_module_size 185 186 dir_cntrl = Directory_Controller(version = i, |
187 directory = RubyDirectoryMemory(version = i, size = dir_size), 188 transitions_per_cycle = options.ports, 189 ruby_system = ruby_system) |
190 191 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 192 dir_cntrl_nodes.append(dir_cntrl) 193 194 # Connect the directory controllers and the network 195 dir_cntrl.requestToDir = MessageBuffer() 196 dir_cntrl.requestToDir.slave = ruby_system.network.master 197 dir_cntrl.responseToDir = MessageBuffer() 198 dir_cntrl.responseToDir.slave = ruby_system.network.master 199 dir_cntrl.responseFromDir = MessageBuffer() 200 dir_cntrl.responseFromDir.master = ruby_system.network.slave 201 dir_cntrl.responseFromMemory = MessageBuffer() 202 203 204 for i, dma_port in enumerate(dma_ports): 205 # Create the Ruby objects associated with the dma controller |
206 dma_seq = DMASequencer(version = i, ruby_system = ruby_system, |
207 slave = dma_port) 208 |
209 dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, |
210 transitions_per_cycle = options.ports, 211 ruby_system = ruby_system) 212 213 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 214 dma_cntrl_nodes.append(dma_cntrl) 215 216 # Connect the dma controller to the network 217 dma_cntrl.mandatoryQueue = MessageBuffer() --- 4 unchanged lines hidden (view full) --- 222 223 all_cntrls = l1_cntrl_nodes + \ 224 l2_cntrl_nodes + \ 225 dir_cntrl_nodes + \ 226 dma_cntrl_nodes 227 228 # Create the io controller and the sequencer 229 if full_system: |
230 io_seq = DMASequencer(version = len(dma_ports), 231 ruby_system = ruby_system) |
232 ruby_system._io_port = io_seq 233 io_controller = DMA_Controller(version = len(dma_ports), 234 dma_sequencer = io_seq, 235 ruby_system = ruby_system) 236 ruby_system.io_controller = io_controller 237 238 # Connect the dma controller to the network 239 io_controller.mandatoryQueue = MessageBuffer() 240 io_controller.responseFromDir = MessageBuffer(ordered = True) 241 io_controller.responseFromDir.slave = ruby_system.network.master 242 io_controller.requestToDir = MessageBuffer() 243 io_controller.requestToDir.master = ruby_system.network.slave 244 245 all_cntrls = all_cntrls + [io_controller] 246 247 ruby_system.network.number_of_virtual_networks = 3 248 topology = create_topology(all_cntrls, options) 249 return (cpu_sequencers, dir_cntrl_nodes, topology) |