1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 148 unchanged lines hidden (view full) --- 157 # Run each of the ruby memory controllers at a ratio of the frequency of 158 # the ruby system 159 # clk_divider value is a fix to pass regression. 160 ruby_system.memctrl_clk_domain = DerivedClockDomain( 161 clk_domain=ruby_system.clk_domain, 162 clk_divider=3) 163 164 for i in xrange(options.num_dirs): |
165 dir_size = MemorySize('0B') 166 dir_size.value = mem_module_size 167 168 dir_cntrl = Directory_Controller(version = i, |
169 directory = RubyDirectoryMemory( 170 version = i, size = dir_size), |
171 transitions_per_cycle = options.ports, 172 ruby_system = ruby_system) 173 174 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 175 dir_cntrl_nodes.append(dir_cntrl) 176 177 # Connect the directory controllers and the network 178 dir_cntrl.requestToDir = ruby_system.network.master --- 44 unchanged lines hidden --- |