1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 94 unchanged lines hidden (view full) --- 103 icache = l1i_cache, 104 dcache = l1d_cache, 105 clk_domain=system.cpu[i].clk_domain, 106 ruby_system = ruby_system) 107 108 l1_cntrl.sequencer = cpu_seq 109 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 110 |
111 # Add controllers and sequencers to the appropriate lists |
112 cpu_sequencers.append(cpu_seq) 113 l1_cntrl_nodes.append(l1_cntrl) 114 |
115 # Connect the L1 controllers and the network 116 l1_cntrl.requestFromL1Cache = ruby_system.network.slave 117 l1_cntrl.responseFromL1Cache = ruby_system.network.slave 118 l1_cntrl.unblockFromL1Cache = ruby_system.network.slave 119 120 l1_cntrl.requestToL1Cache = ruby_system.network.master 121 l1_cntrl.responseToL1Cache = ruby_system.network.master 122 123 |
124 l2_index_start = block_size_bits + l2_bits 125 126 for i in xrange(options.num_l2caches): 127 # 128 # First create the Ruby objects associated with this cpu 129 # 130 l2_cache = L2Cache(size = options.l2_size, 131 assoc = options.l2_assoc, 132 start_index_bit = l2_index_start) 133 134 l2_cntrl = L2Cache_Controller(version = i, 135 L2cache = l2_cache, 136 transitions_per_cycle=options.ports, 137 ruby_system = ruby_system) 138 139 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 140 l2_cntrl_nodes.append(l2_cntrl) 141 |
142 # Connect the L2 controllers and the network 143 l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave 144 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 145 l2_cntrl.responseFromL2Cache = ruby_system.network.slave 146 147 l2_cntrl.unblockToL2Cache = ruby_system.network.master 148 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 149 l2_cntrl.responseToL2Cache = ruby_system.network.master 150 151 |
152 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 153 assert(phys_mem_size % options.num_dirs == 0) 154 mem_module_size = phys_mem_size / options.num_dirs 155 |
156 |
157 # Run each of the ruby memory controllers at a ratio of the frequency of 158 # the ruby system 159 # clk_divider value is a fix to pass regression. 160 ruby_system.memctrl_clk_domain = DerivedClockDomain( 161 clk_domain=ruby_system.clk_domain, 162 clk_divider=3) 163 164 for i in xrange(options.num_dirs): --- 17 unchanged lines hidden (view full) --- 182 options.use_map), 183 memBuffer = mem_cntrl, 184 transitions_per_cycle = options.ports, 185 ruby_system = ruby_system) 186 187 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 188 dir_cntrl_nodes.append(dir_cntrl) 189 |
190 # Connect the directory controllers and the network 191 dir_cntrl.requestToDir = ruby_system.network.master 192 dir_cntrl.responseToDir = ruby_system.network.master 193 dir_cntrl.responseFromDir = ruby_system.network.slave 194 195 |
196 for i, dma_port in enumerate(dma_ports): |
197 # Create the Ruby objects associated with the dma controller |
198 dma_seq = DMASequencer(version = i, 199 ruby_system = ruby_system) 200 201 dma_cntrl = DMA_Controller(version = i, 202 dma_sequencer = dma_seq, 203 transitions_per_cycle = options.ports, 204 ruby_system = ruby_system) 205 206 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 207 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 208 dma_cntrl_nodes.append(dma_cntrl) 209 |
210 # Connect the dma controller to the network 211 dma_cntrl.responseFromDir = ruby_system.network.master 212 dma_cntrl.requestToDir = ruby_system.network.slave 213 214 |
215 all_cntrls = l1_cntrl_nodes + \ 216 l2_cntrl_nodes + \ 217 dir_cntrl_nodes + \ 218 dma_cntrl_nodes 219 220 topology = create_topology(all_cntrls, options) 221 222 return (cpu_sequencers, dir_cntrl_nodes, topology) |