85,86c85,97
< l1_cntrl = L1Cache_Controller(version = i,
< L1Icache = l1i_cache,
---
> # the ruby random tester reuses num_cpus to specify the
> # number of cpu ports connected to the tester object, which
> # is stored in system.cpu. because there is only ever one
> # tester object, num_cpus is not necessarily equal to the
> # size of system.cpu; therefore if len(system.cpu) == 1
> # we use system.cpu[0] to set the clk_domain, thereby ensuring
> # we don't index off the end of the cpu list.
> if len(system.cpu) == 1:
> clk_domain = system.cpu[0].clk_domain
> else:
> clk_domain = system.cpu[i].clk_domain
>
> l1_cntrl = L1Cache_Controller(version = i, L1Icache = l1i_cache,
92,93c103,104
< clk_domain=system.cpu[i].clk_domain,
< transitions_per_cycle=options.ports,
---
> clk_domain = clk_domain,
> transitions_per_cycle = options.ports,
96,99c107,108
< cpu_seq = RubySequencer(version = i,
< icache = l1i_cache,
< dcache = l1d_cache,
< clk_domain=system.cpu[i].clk_domain,
---
> cpu_seq = RubySequencer(version = i, icache = l1i_cache,
> dcache = l1d_cache, clk_domain = clk_domain,
101a111
>
138c148
< transitions_per_cycle=options.ports,
---
> transitions_per_cycle = options.ports,
169,170c179,180
< clk_domain=ruby_system.clk_domain,
< clk_divider=3)
---
> clk_domain = ruby_system.clk_domain,
> clk_divider = 3)
177,180c187,189
< directory = RubyDirectoryMemory(
< version = i, size = dir_size),
< transitions_per_cycle = options.ports,
< ruby_system = ruby_system)
---
> directory = RubyDirectoryMemory(version = i, size = dir_size),
> transitions_per_cycle = options.ports,
> ruby_system = ruby_system)
197,198c206
< dma_seq = DMASequencer(version = i,
< ruby_system = ruby_system,
---
> dma_seq = DMASequencer(version = i, ruby_system = ruby_system,
201,202c209
< dma_cntrl = DMA_Controller(version = i,
< dma_sequencer = dma_seq,
---
> dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq,
223c230,231
< io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
---
> io_seq = DMASequencer(version = len(dma_ports),
> ruby_system = ruby_system)
< l1_cntrl = L1Cache_Controller(version = i,
< L1Icache = l1i_cache,
---
> # the ruby random tester reuses num_cpus to specify the
> # number of cpu ports connected to the tester object, which
> # is stored in system.cpu. because there is only ever one
> # tester object, num_cpus is not necessarily equal to the
> # size of system.cpu; therefore if len(system.cpu) == 1
> # we use system.cpu[0] to set the clk_domain, thereby ensuring
> # we don't index off the end of the cpu list.
> if len(system.cpu) == 1:
> clk_domain = system.cpu[0].clk_domain
> else:
> clk_domain = system.cpu[i].clk_domain
>
> l1_cntrl = L1Cache_Controller(version = i, L1Icache = l1i_cache,
92,93c103,104
< clk_domain=system.cpu[i].clk_domain,
< transitions_per_cycle=options.ports,
---
> clk_domain = clk_domain,
> transitions_per_cycle = options.ports,
96,99c107,108
< cpu_seq = RubySequencer(version = i,
< icache = l1i_cache,
< dcache = l1d_cache,
< clk_domain=system.cpu[i].clk_domain,
---
> cpu_seq = RubySequencer(version = i, icache = l1i_cache,
> dcache = l1d_cache, clk_domain = clk_domain,
101a111
>
138c148
< transitions_per_cycle=options.ports,
---
> transitions_per_cycle = options.ports,
169,170c179,180
< clk_domain=ruby_system.clk_domain,
< clk_divider=3)
---
> clk_domain = ruby_system.clk_domain,
> clk_divider = 3)
177,180c187,189
< directory = RubyDirectoryMemory(
< version = i, size = dir_size),
< transitions_per_cycle = options.ports,
< ruby_system = ruby_system)
---
> directory = RubyDirectoryMemory(version = i, size = dir_size),
> transitions_per_cycle = options.ports,
> ruby_system = ruby_system)
197,198c206
< dma_seq = DMASequencer(version = i,
< ruby_system = ruby_system,
---
> dma_seq = DMASequencer(version = i, ruby_system = ruby_system,
201,202c209
< dma_cntrl = DMA_Controller(version = i,
< dma_sequencer = dma_seq,
---
> dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq,
223c230,231
< io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
---
> io_seq = DMASequencer(version = len(dma_ports),
> ruby_system = ruby_system)