1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40 latency = 3
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 15
47
48def define_options(parser):
49 return
50
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40 latency = 3
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 15
47
48def define_options(parser):
49 return
50
|
51def create_system(options, system, piobus, dma_ports, ruby_system):
| 51def create_system(options, system, dma_ports, ruby_system):
|
52
53 if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
54 fatal("This script requires the MESI_Two_Level protocol to be built.")
55
56 cpu_sequencers = []
57
58 #
59 # The ruby network creation expects the list of nodes in the system to be
60 # consistent with the NetDest list. Therefore the l1 controller nodes must be
61 # listed before the directory nodes and directory nodes before dma nodes, etc.
62 #
63 l1_cntrl_nodes = []
64 l2_cntrl_nodes = []
65 dir_cntrl_nodes = []
66 dma_cntrl_nodes = []
67
68 #
69 # Must create the individual controllers before the network to ensure the
70 # controller constructors are called before the network constructor
71 #
72 l2_bits = int(math.log(options.num_l2caches, 2))
73 block_size_bits = int(math.log(options.cacheline_size, 2))
74
75 for i in xrange(options.num_cpus):
76 #
77 # First create the Ruby objects associated with this cpu
78 #
79 l1i_cache = L1Cache(size = options.l1i_size,
80 assoc = options.l1i_assoc,
81 start_index_bit = block_size_bits,
82 is_icache = True)
83 l1d_cache = L1Cache(size = options.l1d_size,
84 assoc = options.l1d_assoc,
85 start_index_bit = block_size_bits,
86 is_icache = False)
87
88 prefetcher = RubyPrefetcher.Prefetcher()
89
90 l1_cntrl = L1Cache_Controller(version = i,
91 L1Icache = l1i_cache,
92 L1Dcache = l1d_cache,
93 l2_select_num_bits = l2_bits,
94 send_evictions = (
95 options.cpu_type == "detailed"),
96 prefetcher = prefetcher,
97 ruby_system = ruby_system,
98 transitions_per_cycle=options.ports,
99 enable_prefetch = False)
100
101 cpu_seq = RubySequencer(version = i,
102 icache = l1i_cache,
103 dcache = l1d_cache,
104 ruby_system = ruby_system)
105
106 l1_cntrl.sequencer = cpu_seq
| 52
53 if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
54 fatal("This script requires the MESI_Two_Level protocol to be built.")
55
56 cpu_sequencers = []
57
58 #
59 # The ruby network creation expects the list of nodes in the system to be
60 # consistent with the NetDest list. Therefore the l1 controller nodes must be
61 # listed before the directory nodes and directory nodes before dma nodes, etc.
62 #
63 l1_cntrl_nodes = []
64 l2_cntrl_nodes = []
65 dir_cntrl_nodes = []
66 dma_cntrl_nodes = []
67
68 #
69 # Must create the individual controllers before the network to ensure the
70 # controller constructors are called before the network constructor
71 #
72 l2_bits = int(math.log(options.num_l2caches, 2))
73 block_size_bits = int(math.log(options.cacheline_size, 2))
74
75 for i in xrange(options.num_cpus):
76 #
77 # First create the Ruby objects associated with this cpu
78 #
79 l1i_cache = L1Cache(size = options.l1i_size,
80 assoc = options.l1i_assoc,
81 start_index_bit = block_size_bits,
82 is_icache = True)
83 l1d_cache = L1Cache(size = options.l1d_size,
84 assoc = options.l1d_assoc,
85 start_index_bit = block_size_bits,
86 is_icache = False)
87
88 prefetcher = RubyPrefetcher.Prefetcher()
89
90 l1_cntrl = L1Cache_Controller(version = i,
91 L1Icache = l1i_cache,
92 L1Dcache = l1d_cache,
93 l2_select_num_bits = l2_bits,
94 send_evictions = (
95 options.cpu_type == "detailed"),
96 prefetcher = prefetcher,
97 ruby_system = ruby_system,
98 transitions_per_cycle=options.ports,
99 enable_prefetch = False)
100
101 cpu_seq = RubySequencer(version = i,
102 icache = l1i_cache,
103 dcache = l1d_cache,
104 ruby_system = ruby_system)
105
106 l1_cntrl.sequencer = cpu_seq
|
107
108 if piobus != None:
109 cpu_seq.pio_master_port = piobus.slave
110 cpu_seq.mem_master_port = piobus.slave
111 cpu_seq.pio_slave_port = piobus.master
112
| |
113 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
114
115 #
116 # Add controllers and sequencers to the appropriate lists
117 #
118 cpu_sequencers.append(cpu_seq)
119 l1_cntrl_nodes.append(l1_cntrl)
120
121 l2_index_start = block_size_bits + l2_bits
122
123 for i in xrange(options.num_l2caches):
124 #
125 # First create the Ruby objects associated with this cpu
126 #
127 l2_cache = L2Cache(size = options.l2_size,
128 assoc = options.l2_assoc,
129 start_index_bit = l2_index_start)
130
131 l2_cntrl = L2Cache_Controller(version = i,
132 L2cache = l2_cache,
133 transitions_per_cycle=options.ports,
134 ruby_system = ruby_system)
135
136 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
137 l2_cntrl_nodes.append(l2_cntrl)
138
139 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
140 assert(phys_mem_size % options.num_dirs == 0)
141 mem_module_size = phys_mem_size / options.num_dirs
142
143 # Run each of the ruby memory controllers at a ratio of the frequency of
144 # the ruby system
145 # clk_divider value is a fix to pass regression.
146 ruby_system.memctrl_clk_domain = DerivedClockDomain(
147 clk_domain=ruby_system.clk_domain,
148 clk_divider=3)
149
150 for i in xrange(options.num_dirs):
151 #
152 # Create the Ruby objects associated with the directory controller
153 #
154
155 mem_cntrl = RubyMemoryControl(
156 clk_domain = ruby_system.memctrl_clk_domain,
157 version = i,
158 ruby_system = ruby_system)
159
160 dir_size = MemorySize('0B')
161 dir_size.value = mem_module_size
162
163 dir_cntrl = Directory_Controller(version = i,
164 directory = \
165 RubyDirectoryMemory(version = i,
166 size = dir_size,
167 use_map =
168 options.use_map),
169 memBuffer = mem_cntrl,
170 transitions_per_cycle = options.ports,
171 ruby_system = ruby_system)
172
173 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
174 dir_cntrl_nodes.append(dir_cntrl)
175
176 for i, dma_port in enumerate(dma_ports):
177 #
178 # Create the Ruby objects associated with the dma controller
179 #
180 dma_seq = DMASequencer(version = i,
181 ruby_system = ruby_system)
182
183 dma_cntrl = DMA_Controller(version = i,
184 dma_sequencer = dma_seq,
185 transitions_per_cycle = options.ports,
186 ruby_system = ruby_system)
187
188 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
189 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
190 dma_cntrl_nodes.append(dma_cntrl)
191
192 all_cntrls = l1_cntrl_nodes + \
193 l2_cntrl_nodes + \
194 dir_cntrl_nodes + \
195 dma_cntrl_nodes
196
197 topology = create_topology(all_cntrls, options)
198
199 return (cpu_sequencers, dir_cntrl_nodes, topology)
| 107 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
108
109 #
110 # Add controllers and sequencers to the appropriate lists
111 #
112 cpu_sequencers.append(cpu_seq)
113 l1_cntrl_nodes.append(l1_cntrl)
114
115 l2_index_start = block_size_bits + l2_bits
116
117 for i in xrange(options.num_l2caches):
118 #
119 # First create the Ruby objects associated with this cpu
120 #
121 l2_cache = L2Cache(size = options.l2_size,
122 assoc = options.l2_assoc,
123 start_index_bit = l2_index_start)
124
125 l2_cntrl = L2Cache_Controller(version = i,
126 L2cache = l2_cache,
127 transitions_per_cycle=options.ports,
128 ruby_system = ruby_system)
129
130 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
131 l2_cntrl_nodes.append(l2_cntrl)
132
133 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
134 assert(phys_mem_size % options.num_dirs == 0)
135 mem_module_size = phys_mem_size / options.num_dirs
136
137 # Run each of the ruby memory controllers at a ratio of the frequency of
138 # the ruby system
139 # clk_divider value is a fix to pass regression.
140 ruby_system.memctrl_clk_domain = DerivedClockDomain(
141 clk_domain=ruby_system.clk_domain,
142 clk_divider=3)
143
144 for i in xrange(options.num_dirs):
145 #
146 # Create the Ruby objects associated with the directory controller
147 #
148
149 mem_cntrl = RubyMemoryControl(
150 clk_domain = ruby_system.memctrl_clk_domain,
151 version = i,
152 ruby_system = ruby_system)
153
154 dir_size = MemorySize('0B')
155 dir_size.value = mem_module_size
156
157 dir_cntrl = Directory_Controller(version = i,
158 directory = \
159 RubyDirectoryMemory(version = i,
160 size = dir_size,
161 use_map =
162 options.use_map),
163 memBuffer = mem_cntrl,
164 transitions_per_cycle = options.ports,
165 ruby_system = ruby_system)
166
167 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
168 dir_cntrl_nodes.append(dir_cntrl)
169
170 for i, dma_port in enumerate(dma_ports):
171 #
172 # Create the Ruby objects associated with the dma controller
173 #
174 dma_seq = DMASequencer(version = i,
175 ruby_system = ruby_system)
176
177 dma_cntrl = DMA_Controller(version = i,
178 dma_sequencer = dma_seq,
179 transitions_per_cycle = options.ports,
180 ruby_system = ruby_system)
181
182 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
183 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
184 dma_cntrl_nodes.append(dma_cntrl)
185
186 all_cntrls = l1_cntrl_nodes + \
187 l2_cntrl_nodes + \
188 dir_cntrl_nodes + \
189 dma_cntrl_nodes
190
191 topology = create_topology(all_cntrls, options)
192
193 return (cpu_sequencers, dir_cntrl_nodes, topology)
|