MESI_Two_Level.py (11019:fc1e41e88fd3) | MESI_Two_Level.py (11022:e6e3b7097810) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 93 unchanged lines hidden (view full) --- 102 l1_cntrl.sequencer = cpu_seq 103 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 104 105 # Add controllers and sequencers to the appropriate lists 106 cpu_sequencers.append(cpu_seq) 107 l1_cntrl_nodes.append(l1_cntrl) 108 109 # Connect the L1 controllers and the network | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 93 unchanged lines hidden (view full) --- 102 l1_cntrl.sequencer = cpu_seq 103 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 104 105 # Add controllers and sequencers to the appropriate lists 106 cpu_sequencers.append(cpu_seq) 107 l1_cntrl_nodes.append(l1_cntrl) 108 109 # Connect the L1 controllers and the network |
110 l1_cntrl.requestFromL1Cache = ruby_system.network.slave 111 l1_cntrl.responseFromL1Cache = ruby_system.network.slave 112 l1_cntrl.unblockFromL1Cache = ruby_system.network.slave | 110 l1_cntrl.mandatoryQueue = MessageBuffer() 111 l1_cntrl.requestFromL1Cache = MessageBuffer() 112 l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave 113 l1_cntrl.responseFromL1Cache = MessageBuffer() 114 l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave 115 l1_cntrl.unblockFromL1Cache = MessageBuffer() 116 l1_cntrl.unblockFromL1Cache.master = ruby_system.network.slave |
113 | 117 |
114 l1_cntrl.requestToL1Cache = ruby_system.network.master 115 l1_cntrl.responseToL1Cache = ruby_system.network.master | 118 l1_cntrl.optionalQueue = MessageBuffer() |
116 | 119 |
120 l1_cntrl.requestToL1Cache = MessageBuffer() 121 l1_cntrl.requestToL1Cache.slave = ruby_system.network.master 122 l1_cntrl.responseToL1Cache = MessageBuffer() 123 l1_cntrl.responseToL1Cache.slave = ruby_system.network.master |
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117 | 124 |
125 |
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118 l2_index_start = block_size_bits + l2_bits 119 120 for i in xrange(options.num_l2caches): 121 # 122 # First create the Ruby objects associated with this cpu 123 # 124 l2_cache = L2Cache(size = options.l2_size, 125 assoc = options.l2_assoc, 126 start_index_bit = l2_index_start) 127 128 l2_cntrl = L2Cache_Controller(version = i, 129 L2cache = l2_cache, 130 transitions_per_cycle=options.ports, 131 ruby_system = ruby_system) 132 133 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 134 l2_cntrl_nodes.append(l2_cntrl) 135 136 # Connect the L2 controllers and the network | 126 l2_index_start = block_size_bits + l2_bits 127 128 for i in xrange(options.num_l2caches): 129 # 130 # First create the Ruby objects associated with this cpu 131 # 132 l2_cache = L2Cache(size = options.l2_size, 133 assoc = options.l2_assoc, 134 start_index_bit = l2_index_start) 135 136 l2_cntrl = L2Cache_Controller(version = i, 137 L2cache = l2_cache, 138 transitions_per_cycle=options.ports, 139 ruby_system = ruby_system) 140 141 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 142 l2_cntrl_nodes.append(l2_cntrl) 143 144 # Connect the L2 controllers and the network |
137 l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave 138 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 139 l2_cntrl.responseFromL2Cache = ruby_system.network.slave | 145 l2_cntrl.DirRequestFromL2Cache = MessageBuffer() 146 l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave 147 l2_cntrl.L1RequestFromL2Cache = MessageBuffer() 148 l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave 149 l2_cntrl.responseFromL2Cache = MessageBuffer() 150 l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave |
140 | 151 |
141 l2_cntrl.unblockToL2Cache = ruby_system.network.master 142 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 143 l2_cntrl.responseToL2Cache = ruby_system.network.master | 152 l2_cntrl.unblockToL2Cache = MessageBuffer() 153 l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master 154 l2_cntrl.L1RequestToL2Cache = MessageBuffer() 155 l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master 156 l2_cntrl.responseToL2Cache = MessageBuffer() 157 l2_cntrl.responseToL2Cache.slave = ruby_system.network.master |
144 145 146 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 147 assert(phys_mem_size % options.num_dirs == 0) 148 mem_module_size = phys_mem_size / options.num_dirs 149 150 151 # Run each of the ruby memory controllers at a ratio of the frequency of --- 12 unchanged lines hidden (view full) --- 164 version = i, size = dir_size), 165 transitions_per_cycle = options.ports, 166 ruby_system = ruby_system) 167 168 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 169 dir_cntrl_nodes.append(dir_cntrl) 170 171 # Connect the directory controllers and the network | 158 159 160 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 161 assert(phys_mem_size % options.num_dirs == 0) 162 mem_module_size = phys_mem_size / options.num_dirs 163 164 165 # Run each of the ruby memory controllers at a ratio of the frequency of --- 12 unchanged lines hidden (view full) --- 178 version = i, size = dir_size), 179 transitions_per_cycle = options.ports, 180 ruby_system = ruby_system) 181 182 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 183 dir_cntrl_nodes.append(dir_cntrl) 184 185 # Connect the directory controllers and the network |
172 dir_cntrl.requestToDir = ruby_system.network.master 173 dir_cntrl.responseToDir = ruby_system.network.master 174 dir_cntrl.responseFromDir = ruby_system.network.slave | 186 dir_cntrl.requestToDir = MessageBuffer() 187 dir_cntrl.requestToDir.slave = ruby_system.network.master 188 dir_cntrl.responseToDir = MessageBuffer() 189 dir_cntrl.responseToDir.slave = ruby_system.network.master 190 dir_cntrl.responseFromDir = MessageBuffer() 191 dir_cntrl.responseFromDir.master = ruby_system.network.slave 192 dir_cntrl.responseFromMemory = MessageBuffer() |
175 176 177 for i, dma_port in enumerate(dma_ports): 178 # Create the Ruby objects associated with the dma controller 179 dma_seq = DMASequencer(version = i, 180 ruby_system = ruby_system, 181 slave = dma_port) 182 183 dma_cntrl = DMA_Controller(version = i, 184 dma_sequencer = dma_seq, 185 transitions_per_cycle = options.ports, 186 ruby_system = ruby_system) 187 188 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 189 dma_cntrl_nodes.append(dma_cntrl) 190 191 # Connect the dma controller to the network | 193 194 195 for i, dma_port in enumerate(dma_ports): 196 # Create the Ruby objects associated with the dma controller 197 dma_seq = DMASequencer(version = i, 198 ruby_system = ruby_system, 199 slave = dma_port) 200 201 dma_cntrl = DMA_Controller(version = i, 202 dma_sequencer = dma_seq, 203 transitions_per_cycle = options.ports, 204 ruby_system = ruby_system) 205 206 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 207 dma_cntrl_nodes.append(dma_cntrl) 208 209 # Connect the dma controller to the network |
192 dma_cntrl.responseFromDir = ruby_system.network.master 193 dma_cntrl.requestToDir = ruby_system.network.slave | 210 dma_cntrl.mandatoryQueue = MessageBuffer() 211 dma_cntrl.responseFromDir = MessageBuffer(ordered = True) 212 dma_cntrl.responseFromDir.slave = ruby_system.network.master 213 dma_cntrl.requestToDir = MessageBuffer() 214 dma_cntrl.requestToDir.master = ruby_system.network.slave |
194 195 all_cntrls = l1_cntrl_nodes + \ 196 l2_cntrl_nodes + \ 197 dir_cntrl_nodes + \ 198 dma_cntrl_nodes 199 200 # Create the io controller and the sequencer 201 if full_system: 202 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 203 ruby_system._io_port = io_seq 204 io_controller = DMA_Controller(version = len(dma_ports), 205 dma_sequencer = io_seq, 206 ruby_system = ruby_system) 207 ruby_system.io_controller = io_controller 208 209 # Connect the dma controller to the network | 215 216 all_cntrls = l1_cntrl_nodes + \ 217 l2_cntrl_nodes + \ 218 dir_cntrl_nodes + \ 219 dma_cntrl_nodes 220 221 # Create the io controller and the sequencer 222 if full_system: 223 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 224 ruby_system._io_port = io_seq 225 io_controller = DMA_Controller(version = len(dma_ports), 226 dma_sequencer = io_seq, 227 ruby_system = ruby_system) 228 ruby_system.io_controller = io_controller 229 230 # Connect the dma controller to the network |
210 io_controller.responseFromDir = ruby_system.network.master 211 io_controller.requestToDir = ruby_system.network.slave | 231 io_controller.mandatoryQueue = MessageBuffer() 232 io_controller.responseFromDir = MessageBuffer(ordered = True) 233 io_controller.responseFromDir.slave = ruby_system.network.master 234 io_controller.requestToDir = MessageBuffer() 235 io_controller.requestToDir.master = ruby_system.network.slave |
212 213 all_cntrls = all_cntrls + [io_controller] 214 215 topology = create_topology(all_cntrls, options) 216 return (cpu_sequencers, dir_cntrl_nodes, topology) | 236 237 all_cntrls = all_cntrls + [io_controller] 238 239 topology = create_topology(all_cntrls, options) 240 return (cpu_sequencers, dir_cntrl_nodes, topology) |