1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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102 l1_cntrl.sequencer = cpu_seq
103 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
104
105 # Add controllers and sequencers to the appropriate lists
106 cpu_sequencers.append(cpu_seq)
107 l1_cntrl_nodes.append(l1_cntrl)
108
109 # Connect the L1 controllers and the network
110 l1_cntrl.requestFromL1Cache = ruby_system.network.slave
111 l1_cntrl.responseFromL1Cache = ruby_system.network.slave
112 l1_cntrl.unblockFromL1Cache = ruby_system.network.slave
113
114 l1_cntrl.requestToL1Cache = ruby_system.network.master
115 l1_cntrl.responseToL1Cache = ruby_system.network.master
116
117
118 l2_index_start = block_size_bits + l2_bits
119
120 for i in xrange(options.num_l2caches):
121 #
122 # First create the Ruby objects associated with this cpu
123 #
124 l2_cache = L2Cache(size = options.l2_size,
125 assoc = options.l2_assoc,
126 start_index_bit = l2_index_start)
127
128 l2_cntrl = L2Cache_Controller(version = i,
129 L2cache = l2_cache,
130 transitions_per_cycle=options.ports,
131 ruby_system = ruby_system)
132
133 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
134 l2_cntrl_nodes.append(l2_cntrl)
135
136 # Connect the L2 controllers and the network
137 l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave
138 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
139 l2_cntrl.responseFromL2Cache = ruby_system.network.slave
140
141 l2_cntrl.unblockToL2Cache = ruby_system.network.master
142 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
143 l2_cntrl.responseToL2Cache = ruby_system.network.master
144
145
146 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
147 assert(phys_mem_size % options.num_dirs == 0)
148 mem_module_size = phys_mem_size / options.num_dirs
149
150
151 # Run each of the ruby memory controllers at a ratio of the frequency of

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164 version = i, size = dir_size),
165 transitions_per_cycle = options.ports,
166 ruby_system = ruby_system)
167
168 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
169 dir_cntrl_nodes.append(dir_cntrl)
170
171 # Connect the directory controllers and the network
172 dir_cntrl.requestToDir = ruby_system.network.master
173 dir_cntrl.responseToDir = ruby_system.network.master
174 dir_cntrl.responseFromDir = ruby_system.network.slave
175
176
177 for i, dma_port in enumerate(dma_ports):
178 # Create the Ruby objects associated with the dma controller
179 dma_seq = DMASequencer(version = i,
180 ruby_system = ruby_system,
181 slave = dma_port)
182
183 dma_cntrl = DMA_Controller(version = i,
184 dma_sequencer = dma_seq,
185 transitions_per_cycle = options.ports,
186 ruby_system = ruby_system)
187
188 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
189 dma_cntrl_nodes.append(dma_cntrl)
190
191 # Connect the dma controller to the network
192 dma_cntrl.responseFromDir = ruby_system.network.master
193 dma_cntrl.requestToDir = ruby_system.network.slave
194
195 all_cntrls = l1_cntrl_nodes + \
196 l2_cntrl_nodes + \
197 dir_cntrl_nodes + \
198 dma_cntrl_nodes
199
200 # Create the io controller and the sequencer
201 if full_system:
202 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
203 ruby_system._io_port = io_seq
204 io_controller = DMA_Controller(version = len(dma_ports),
205 dma_sequencer = io_seq,
206 ruby_system = ruby_system)
207 ruby_system.io_controller = io_controller
208
209 # Connect the dma controller to the network
210 io_controller.responseFromDir = ruby_system.network.master
211 io_controller.requestToDir = ruby_system.network.slave
212
213 all_cntrls = all_cntrls + [io_controller]
214
215 topology = create_topology(all_cntrls, options)
216 return (cpu_sequencers, dir_cntrl_nodes, topology)