1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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157 # Run each of the ruby memory controllers at a ratio of the frequency of
158 # the ruby system
159 # clk_divider value is a fix to pass regression.
160 ruby_system.memctrl_clk_domain = DerivedClockDomain(
161 clk_domain=ruby_system.clk_domain,
162 clk_divider=3)
163
164 for i in xrange(options.num_dirs):
165 #
166 # Create the Ruby objects associated with the directory controller
167 #
168
169 mem_cntrl = RubyMemoryControl(
170 clk_domain = ruby_system.memctrl_clk_domain,
171 version = i,
172 ruby_system = ruby_system)
173
174 dir_size = MemorySize('0B')
175 dir_size.value = mem_module_size
176
177 dir_cntrl = Directory_Controller(version = i,
178 directory = \
179 RubyDirectoryMemory(version = i,
180 size = dir_size,
181 use_map =
182 options.use_map),
183 memBuffer = mem_cntrl,
184 transitions_per_cycle = options.ports,
185 ruby_system = ruby_system)
186
187 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
188 dir_cntrl_nodes.append(dir_cntrl)
189
190 # Connect the directory controllers and the network
191 dir_cntrl.requestToDir = ruby_system.network.master

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