| MESI_Three_Level.py (11019:fc1e41e88fd3) | MESI_Three_Level.py (11022:e6e3b7097810) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# Copyright (c) 2013 Mark D. Hill and David A. Wood 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 113 unchanged lines hidden (view full) --- 122 # 123 # Add controllers and sequencers to the appropriate lists 124 # 125 cpu_sequencers.append(cpu_seq) 126 l0_cntrl_nodes.append(l0_cntrl) 127 l1_cntrl_nodes.append(l1_cntrl) 128 129 # Connect the L0 and L1 controllers | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# Copyright (c) 2013 Mark D. Hill and David A. Wood 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 113 unchanged lines hidden (view full) --- 122 # 123 # Add controllers and sequencers to the appropriate lists 124 # 125 cpu_sequencers.append(cpu_seq) 126 l0_cntrl_nodes.append(l0_cntrl) 127 l1_cntrl_nodes.append(l1_cntrl) 128 129 # Connect the L0 and L1 controllers |
| 130 l0_cntrl.bufferToL1 = l1_cntrl.bufferFromL0 131 l0_cntrl.bufferFromL1 = l1_cntrl.bufferToL0 | 130 l0_cntrl.mandatoryQueue = MessageBuffer() 131 l0_cntrl.bufferToL1 = MessageBuffer(ordered = True) 132 l1_cntrl.bufferFromL0 = l0_cntrl.bufferToL1 133 l0_cntrl.bufferFromL1 = MessageBuffer(ordered = True) 134 l1_cntrl.bufferToL0 = l0_cntrl.bufferFromL1 |
| 132 133 # Connect the L1 controllers and the network | 135 136 # Connect the L1 controllers and the network |
| 134 l1_cntrl.requestToL2 = ruby_system.network.slave 135 l1_cntrl.responseToL2 = ruby_system.network.slave 136 l1_cntrl.unblockToL2 = ruby_system.network.slave | 137 l1_cntrl.requestToL2 = MessageBuffer() 138 l1_cntrl.requestToL2.master = ruby_system.network.slave 139 l1_cntrl.responseToL2 = MessageBuffer() 140 l1_cntrl.responseToL2.master = ruby_system.network.slave 141 l1_cntrl.unblockToL2 = MessageBuffer() 142 l1_cntrl.unblockToL2.master = ruby_system.network.slave |
| 137 | 143 |
| 138 l1_cntrl.requestFromL2 = ruby_system.network.master 139 l1_cntrl.responseFromL2 = ruby_system.network.master | 144 l1_cntrl.requestFromL2 = MessageBuffer() 145 l1_cntrl.requestFromL2.slave = ruby_system.network.master 146 l1_cntrl.responseFromL2 = MessageBuffer() 147 l1_cntrl.responseFromL2.slave = ruby_system.network.master |
| 140 141 142 for j in xrange(num_l2caches_per_cluster): 143 l2_cache = L2Cache(size = options.l2_size, 144 assoc = options.l2_assoc, 145 start_index_bit = l2_index_start) 146 147 l2_cntrl = L2Cache_Controller( 148 version = i * num_l2caches_per_cluster + j, 149 L2cache = l2_cache, cluster_id = i, 150 transitions_per_cycle=options.ports, 151 ruby_system = ruby_system) 152 153 exec("ruby_system.l2_cntrl%d = l2_cntrl" % ( 154 i * num_l2caches_per_cluster + j)) 155 l2_cntrl_nodes.append(l2_cntrl) 156 157 # Connect the L2 controllers and the network | 148 149 150 for j in xrange(num_l2caches_per_cluster): 151 l2_cache = L2Cache(size = options.l2_size, 152 assoc = options.l2_assoc, 153 start_index_bit = l2_index_start) 154 155 l2_cntrl = L2Cache_Controller( 156 version = i * num_l2caches_per_cluster + j, 157 L2cache = l2_cache, cluster_id = i, 158 transitions_per_cycle=options.ports, 159 ruby_system = ruby_system) 160 161 exec("ruby_system.l2_cntrl%d = l2_cntrl" % ( 162 i * num_l2caches_per_cluster + j)) 163 l2_cntrl_nodes.append(l2_cntrl) 164 165 # Connect the L2 controllers and the network |
| 158 l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave 159 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 160 l2_cntrl.responseFromL2Cache = ruby_system.network.slave | 166 l2_cntrl.DirRequestFromL2Cache = MessageBuffer() 167 l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave 168 l2_cntrl.L1RequestFromL2Cache = MessageBuffer() 169 l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave 170 l2_cntrl.responseFromL2Cache = MessageBuffer() 171 l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave |
| 161 | 172 |
| 162 l2_cntrl.unblockToL2Cache = ruby_system.network.master 163 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 164 l2_cntrl.responseToL2Cache = ruby_system.network.master | 173 l2_cntrl.unblockToL2Cache = MessageBuffer() 174 l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master 175 l2_cntrl.L1RequestToL2Cache = MessageBuffer() 176 l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master 177 l2_cntrl.responseToL2Cache = MessageBuffer() 178 l2_cntrl.responseToL2Cache.slave = ruby_system.network.master |
| 165 166 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 167 assert(phys_mem_size % options.num_dirs == 0) 168 mem_module_size = phys_mem_size / options.num_dirs 169 170 # Run each of the ruby memory controllers at a ratio of the frequency of 171 # the ruby system 172 # clk_divider value is a fix to pass regression. --- 13 unchanged lines hidden (view full) --- 186 version = i, size = dir_size), 187 transitions_per_cycle = options.ports, 188 ruby_system = ruby_system) 189 190 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 191 dir_cntrl_nodes.append(dir_cntrl) 192 193 # Connect the directory controllers and the network | 179 180 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 181 assert(phys_mem_size % options.num_dirs == 0) 182 mem_module_size = phys_mem_size / options.num_dirs 183 184 # Run each of the ruby memory controllers at a ratio of the frequency of 185 # the ruby system 186 # clk_divider value is a fix to pass regression. --- 13 unchanged lines hidden (view full) --- 200 version = i, size = dir_size), 201 transitions_per_cycle = options.ports, 202 ruby_system = ruby_system) 203 204 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 205 dir_cntrl_nodes.append(dir_cntrl) 206 207 # Connect the directory controllers and the network |
| 194 dir_cntrl.requestToDir = ruby_system.network.master 195 dir_cntrl.responseToDir = ruby_system.network.master 196 dir_cntrl.responseFromDir = ruby_system.network.slave | 208 dir_cntrl.requestToDir = MessageBuffer() 209 dir_cntrl.requestToDir.slave = ruby_system.network.master 210 dir_cntrl.responseToDir = MessageBuffer() 211 dir_cntrl.responseToDir.slave = ruby_system.network.master 212 dir_cntrl.responseFromDir = MessageBuffer() 213 dir_cntrl.responseFromDir.master = ruby_system.network.slave 214 dir_cntrl.responseFromMemory = MessageBuffer() |
| 197 198 for i, dma_port in enumerate(dma_ports): 199 # 200 # Create the Ruby objects associated with the dma controller 201 # 202 dma_seq = DMASequencer(version = i, 203 ruby_system = ruby_system) 204 205 dma_cntrl = DMA_Controller(version = i, 206 dma_sequencer = dma_seq, 207 transitions_per_cycle = options.ports, 208 ruby_system = ruby_system) 209 210 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 211 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 212 dma_cntrl_nodes.append(dma_cntrl) 213 214 # Connect the dma controller to the network | 215 216 for i, dma_port in enumerate(dma_ports): 217 # 218 # Create the Ruby objects associated with the dma controller 219 # 220 dma_seq = DMASequencer(version = i, 221 ruby_system = ruby_system) 222 223 dma_cntrl = DMA_Controller(version = i, 224 dma_sequencer = dma_seq, 225 transitions_per_cycle = options.ports, 226 ruby_system = ruby_system) 227 228 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 229 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 230 dma_cntrl_nodes.append(dma_cntrl) 231 232 # Connect the dma controller to the network |
| 215 dma_cntrl.responseFromDir = ruby_system.network.master 216 dma_cntrl.requestToDir = ruby_system.network.slave | 233 dma_cntrl.mandatoryQueue = MessageBuffer() 234 dma_cntrl.responseFromDir = MessageBuffer(ordered = True) 235 dma_cntrl.responseFromDir.slave = ruby_system.network.master 236 dma_cntrl.requestToDir = MessageBuffer() 237 dma_cntrl.requestToDir.master = ruby_system.network.slave |
| 217 218 all_cntrls = l0_cntrl_nodes + \ 219 l1_cntrl_nodes + \ 220 l2_cntrl_nodes + \ 221 dir_cntrl_nodes + \ 222 dma_cntrl_nodes 223 224 # Create the io controller and the sequencer 225 if full_system: 226 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 227 ruby_system._io_port = io_seq 228 io_controller = DMA_Controller(version = len(dma_ports), 229 dma_sequencer = io_seq, 230 ruby_system = ruby_system) 231 ruby_system.io_controller = io_controller 232 233 # Connect the dma controller to the network | 238 239 all_cntrls = l0_cntrl_nodes + \ 240 l1_cntrl_nodes + \ 241 l2_cntrl_nodes + \ 242 dir_cntrl_nodes + \ 243 dma_cntrl_nodes 244 245 # Create the io controller and the sequencer 246 if full_system: 247 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 248 ruby_system._io_port = io_seq 249 io_controller = DMA_Controller(version = len(dma_ports), 250 dma_sequencer = io_seq, 251 ruby_system = ruby_system) 252 ruby_system.io_controller = io_controller 253 254 # Connect the dma controller to the network |
| 234 io_controller.responseFromDir = ruby_system.network.master 235 io_controller.requestToDir = ruby_system.network.slave | 255 io_controller.mandatoryQueue = MessageBuffer() 256 io_controller.responseFromDir = MessageBuffer(ordered = True) 257 io_controller.responseFromDir.slave = ruby_system.network.master 258 io_controller.requestToDir = MessageBuffer() 259 io_controller.requestToDir.master = ruby_system.network.slave |
| 236 237 all_cntrls = all_cntrls + [io_controller] 238 239 topology = create_topology(all_cntrls, options) 240 return (cpu_sequencers, dir_cntrl_nodes, topology) | 260 261 all_cntrls = all_cntrls + [io_controller] 262 263 topology = create_topology(all_cntrls, options) 264 return (cpu_sequencers, dir_cntrl_nodes, topology) |