MESI_Three_Level.py (10970:ea8bdb1d9f1e) MESI_Three_Level.py (10988:ede920fb4f66)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# Copyright (c) 2013 Mark D. Hill and David A. Wood
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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103 replacement_policy = LRUReplacementPolicy())
104
105 l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j,
106 Icache = l0i_cache, Dcache = l0d_cache,
107 send_evictions = send_evicts(options),
108 clk_domain=system.cpu[i].clk_domain,
109 ruby_system = ruby_system)
110
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# Copyright (c) 2013 Mark D. Hill and David A. Wood
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 94 unchanged lines hidden (view full) ---

103 replacement_policy = LRUReplacementPolicy())
104
105 l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j,
106 Icache = l0i_cache, Dcache = l0d_cache,
107 send_evictions = send_evicts(options),
108 clk_domain=system.cpu[i].clk_domain,
109 ruby_system = ruby_system)
110
111 cpu_seq = RubySequencer(version = i, icache = l0i_cache,
111 cpu_seq = RubySequencer(version = i * num_cpus_per_cluster + j,
112 icache = l0i_cache,
112 clk_domain=system.cpu[i].clk_domain,
113 dcache = l0d_cache, ruby_system = ruby_system)
114
115 l0_cntrl.sequencer = cpu_seq
116
117 l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc,
118 start_index_bit = block_size_bits, is_icache = False)
119

--- 128 unchanged lines hidden --- 		113 clk_domain=system.cpu[i].clk_domain,
114 dcache = l0d_cache, ruby_system = ruby_system)
115
116 l0_cntrl.sequencer = cpu_seq
117
118 l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc,
119 start_index_bit = block_size_bits, is_icache = False)
120

--- 128 unchanged lines hidden ---