| MESI_Three_Level.py (10300:ed3816dae6d5) | MESI_Three_Level.py (10311:ad9c042dce54) |
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| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# Copyright (c) 2013 Mark D. Hill and David A. Wood 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 115 unchanged lines hidden (view full) --- 124 i*num_cpus_per_cluster+j)) 125 126 # 127 # Add controllers and sequencers to the appropriate lists 128 # 129 cpu_sequencers.append(cpu_seq) 130 l0_cntrl_nodes.append(l0_cntrl) 131 l1_cntrl_nodes.append(l1_cntrl) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# Copyright (c) 2013 Mark D. Hill and David A. Wood 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 115 unchanged lines hidden (view full) --- 124 i*num_cpus_per_cluster+j)) 125 126 # 127 # Add controllers and sequencers to the appropriate lists 128 # 129 cpu_sequencers.append(cpu_seq) 130 l0_cntrl_nodes.append(l0_cntrl) 131 l1_cntrl_nodes.append(l1_cntrl) |
| 132 l0_cntrl.peer = l1_cntrl | |
| 133 | 132 |
| 133 # Connect the L0 and L1 controllers 134 l0_cntrl.bufferToL1 = l1_cntrl.bufferFromL0 135 l0_cntrl.bufferFromL1 = l1_cntrl.bufferToL0 136 137 # Connect the L1 controllers and the network 138 l1_cntrl.requestToL2 = ruby_system.network.slave 139 l1_cntrl.responseToL2 = ruby_system.network.slave 140 l1_cntrl.unblockToL2 = ruby_system.network.slave 141 142 l1_cntrl.requestFromL2 = ruby_system.network.master 143 l1_cntrl.responseFromL2 = ruby_system.network.master 144 145 |
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| 134 for j in xrange(num_l2caches_per_cluster): 135 l2_cache = L2Cache(size = options.l2_size, 136 assoc = options.l2_assoc, 137 start_index_bit = l2_index_start) 138 139 l2_cntrl = L2Cache_Controller( 140 version = i * num_l2caches_per_cluster + j, 141 L2cache = l2_cache, cluster_id = i, 142 transitions_per_cycle=options.ports, 143 ruby_system = ruby_system) 144 145 exec("ruby_system.l2_cntrl%d = l2_cntrl" % ( 146 i * num_l2caches_per_cluster + j)) 147 l2_cntrl_nodes.append(l2_cntrl) 148 | 146 for j in xrange(num_l2caches_per_cluster): 147 l2_cache = L2Cache(size = options.l2_size, 148 assoc = options.l2_assoc, 149 start_index_bit = l2_index_start) 150 151 l2_cntrl = L2Cache_Controller( 152 version = i * num_l2caches_per_cluster + j, 153 L2cache = l2_cache, cluster_id = i, 154 transitions_per_cycle=options.ports, 155 ruby_system = ruby_system) 156 157 exec("ruby_system.l2_cntrl%d = l2_cntrl" % ( 158 i * num_l2caches_per_cluster + j)) 159 l2_cntrl_nodes.append(l2_cntrl) 160 |
| 161 # Connect the L2 controllers and the network 162 l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave 163 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 164 l2_cntrl.responseFromL2Cache = ruby_system.network.slave 165 166 l2_cntrl.unblockToL2Cache = ruby_system.network.master 167 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 168 l2_cntrl.responseToL2Cache = ruby_system.network.master 169 |
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| 149 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 150 assert(phys_mem_size % options.num_dirs == 0) 151 mem_module_size = phys_mem_size / options.num_dirs 152 153 # Run each of the ruby memory controllers at a ratio of the frequency of 154 # the ruby system 155 # clk_divider value is a fix to pass regression. 156 ruby_system.memctrl_clk_domain = DerivedClockDomain( --- 21 unchanged lines hidden (view full) --- 178 options.use_map), 179 memBuffer = mem_cntrl, 180 transitions_per_cycle = options.ports, 181 ruby_system = ruby_system) 182 183 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 184 dir_cntrl_nodes.append(dir_cntrl) 185 | 170 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 171 assert(phys_mem_size % options.num_dirs == 0) 172 mem_module_size = phys_mem_size / options.num_dirs 173 174 # Run each of the ruby memory controllers at a ratio of the frequency of 175 # the ruby system 176 # clk_divider value is a fix to pass regression. 177 ruby_system.memctrl_clk_domain = DerivedClockDomain( --- 21 unchanged lines hidden (view full) --- 199 options.use_map), 200 memBuffer = mem_cntrl, 201 transitions_per_cycle = options.ports, 202 ruby_system = ruby_system) 203 204 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 205 dir_cntrl_nodes.append(dir_cntrl) 206 |
| 207 # Connect the directory controllers and the network 208 dir_cntrl.requestToDir = ruby_system.network.master 209 dir_cntrl.responseToDir = ruby_system.network.master 210 dir_cntrl.responseFromDir = ruby_system.network.slave 211 |
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| 186 for i, dma_port in enumerate(dma_ports): 187 # 188 # Create the Ruby objects associated with the dma controller 189 # 190 dma_seq = DMASequencer(version = i, 191 ruby_system = ruby_system) 192 193 dma_cntrl = DMA_Controller(version = i, --- 16 unchanged lines hidden --- | 212 for i, dma_port in enumerate(dma_ports): 213 # 214 # Create the Ruby objects associated with the dma controller 215 # 216 dma_seq = DMASequencer(version = i, 217 ruby_system = ruby_system) 218 219 dma_cntrl = DMA_Controller(version = i, --- 16 unchanged lines hidden --- |