1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009,2015 Advanced Micro Devices, Inc. 3# Copyright (c) 2013 Mark D. Hill and David A. Wood 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 187 unchanged lines hidden (view full) --- 196 197 # Run each of the ruby memory controllers at a ratio of the frequency of 198 # the ruby system 199 # clk_divider value is a fix to pass regression. 200 ruby_system.memctrl_clk_domain = DerivedClockDomain( 201 clk_domain = ruby_system.clk_domain, clk_divider = 3) 202 203 mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( |
204 options, bootmem, ruby_system, system) |
205 dir_cntrl_nodes = mem_dir_cntrl_nodes[:] 206 if rom_dir_cntrl_node is not None: 207 dir_cntrl_nodes.append(rom_dir_cntrl_node) 208 for dir_cntrl in dir_cntrl_nodes: 209 # Connect the directory controllers and the network 210 dir_cntrl.requestToDir = MessageBuffer() 211 dir_cntrl.requestToDir.slave = ruby_system.network.master 212 dir_cntrl.responseToDir = MessageBuffer() --- 54 unchanged lines hidden --- |