1# Copyright (c) 2006-2007 The Regents of The University of Michigan |
2# Copyright (c) 2009,2015 Advanced Micro Devices, Inc. |
3# Copyright (c) 2013 Mark D. Hill and David A. Wood 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright 9# notice, this list of conditions and the following disclaimer; 10# redistributions in binary form must reproduce the above copyright --- 28 unchanged lines hidden (view full) --- 39# 40# Declare caches used by the protocol 41# 42class L0Cache(RubyCache): pass 43class L1Cache(RubyCache): pass 44class L2Cache(RubyCache): pass 45 46def define_options(parser): |
47 parser.add_option("--num-clusters", type = "int", default = 1, 48 help = "number of clusters in a design in which there are shared\ |
49 caches private to clusters") 50 return 51 52def create_system(options, full_system, system, dma_ports, ruby_system): 53 54 if buildEnv['PROTOCOL'] != 'MESI_Three_Level': |
55 fatal("This script requires the MESI_Three_Level protocol to be\ 56 built.") |
57 58 cpu_sequencers = [] 59 60 # 61 # The ruby network creation expects the list of nodes in the system to be |
62 # consistent with the NetDest list. Therefore the l1 controller nodes 63 # must be listed before the directory nodes and directory nodes before 64 # dma nodes, etc. |
65 # 66 l0_cntrl_nodes = [] 67 l1_cntrl_nodes = [] 68 l2_cntrl_nodes = [] 69 dir_cntrl_nodes = [] 70 dma_cntrl_nodes = [] 71 72 assert (options.num_cpus % options.num_clusters == 0) --- 18 unchanged lines hidden (view full) --- 91 l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True, 92 start_index_bit = block_size_bits, 93 replacement_policy = LRUReplacementPolicy()) 94 95 l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False, 96 start_index_bit = block_size_bits, 97 replacement_policy = LRUReplacementPolicy()) 98 |
99 # the ruby random tester reuses num_cpus to specify the 100 # number of cpu ports connected to the tester object, which 101 # is stored in system.cpu. because there is only ever one 102 # tester object, num_cpus is not necessarily equal to the 103 # size of system.cpu; therefore if len(system.cpu) == 1 104 # we use system.cpu[0] to set the clk_domain, thereby ensuring 105 # we don't index off the end of the cpu list. 106 if len(system.cpu) == 1: 107 clk_domain = system.cpu[0].clk_domain 108 else: 109 clk_domain = system.cpu[i].clk_domain |
110 |
111 l0_cntrl = L0Cache_Controller( 112 version = i * num_cpus_per_cluster + j, Icache = l0i_cache, 113 Dcache = l0d_cache, send_evictions = send_evicts(options), 114 clk_domain = clk_domain, ruby_system = ruby_system) 115 |
116 cpu_seq = RubySequencer(version = i * num_cpus_per_cluster + j, |
117 icache = l0i_cache, 118 clk_domain = clk_domain, 119 dcache = l0d_cache, 120 ruby_system = ruby_system) |
121 122 l0_cntrl.sequencer = cpu_seq 123 |
124 l1_cache = L1Cache(size = options.l1d_size, 125 assoc = options.l1d_assoc, 126 start_index_bit = block_size_bits, 127 is_icache = False) |
128 |
129 l1_cntrl = L1Cache_Controller( 130 version = i * num_cpus_per_cluster + j, 131 cache = l1_cache, l2_select_num_bits = l2_bits, 132 cluster_id = i, ruby_system = ruby_system) |
133 |
134 exec("ruby_system.l0_cntrl%d = l0_cntrl" 135 % ( i * num_cpus_per_cluster + j)) 136 exec("ruby_system.l1_cntrl%d = l1_cntrl" 137 % ( i * num_cpus_per_cluster + j)) |
138 139 # 140 # Add controllers and sequencers to the appropriate lists 141 # 142 cpu_sequencers.append(cpu_seq) 143 l0_cntrl_nodes.append(l0_cntrl) 144 l1_cntrl_nodes.append(l1_cntrl) 145 --- 21 unchanged lines hidden (view full) --- 167 for j in xrange(num_l2caches_per_cluster): 168 l2_cache = L2Cache(size = options.l2_size, 169 assoc = options.l2_assoc, 170 start_index_bit = l2_index_start) 171 172 l2_cntrl = L2Cache_Controller( 173 version = i * num_l2caches_per_cluster + j, 174 L2cache = l2_cache, cluster_id = i, |
175 transitions_per_cycle = options.ports, |
176 ruby_system = ruby_system) 177 |
178 exec("ruby_system.l2_cntrl%d = l2_cntrl" 179 % (i * num_l2caches_per_cluster + j)) |
180 l2_cntrl_nodes.append(l2_cntrl) 181 182 # Connect the L2 controllers and the network 183 l2_cntrl.DirRequestFromL2Cache = MessageBuffer() 184 l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave 185 l2_cntrl.L1RequestFromL2Cache = MessageBuffer() 186 l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave 187 l2_cntrl.responseFromL2Cache = MessageBuffer() --- 9 unchanged lines hidden (view full) --- 197 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 198 assert(phys_mem_size % options.num_dirs == 0) 199 mem_module_size = phys_mem_size / options.num_dirs 200 201 # Run each of the ruby memory controllers at a ratio of the frequency of 202 # the ruby system 203 # clk_divider value is a fix to pass regression. 204 ruby_system.memctrl_clk_domain = DerivedClockDomain( |
205 clk_domain = ruby_system.clk_domain, clk_divider = 3) |
206 207 for i in xrange(options.num_dirs): 208 # 209 # Create the Ruby objects associated with the directory controller 210 # 211 dir_size = MemorySize('0B') 212 dir_size.value = mem_module_size 213 214 dir_cntrl = Directory_Controller(version = i, |
215 directory = RubyDirectoryMemory(version = i, size = dir_size), 216 transitions_per_cycle = options.ports, 217 ruby_system = ruby_system) |
218 219 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 220 dir_cntrl_nodes.append(dir_cntrl) 221 222 # Connect the directory controllers and the network 223 dir_cntrl.requestToDir = MessageBuffer() 224 dir_cntrl.requestToDir.slave = ruby_system.network.master 225 dir_cntrl.responseToDir = MessageBuffer() 226 dir_cntrl.responseToDir.slave = ruby_system.network.master 227 dir_cntrl.responseFromDir = MessageBuffer() 228 dir_cntrl.responseFromDir.master = ruby_system.network.slave 229 dir_cntrl.responseFromMemory = MessageBuffer() 230 231 for i, dma_port in enumerate(dma_ports): 232 # 233 # Create the Ruby objects associated with the dma controller 234 # |
235 dma_seq = DMASequencer(version = i, ruby_system = ruby_system) |
236 237 dma_cntrl = DMA_Controller(version = i, 238 dma_sequencer = dma_seq, 239 transitions_per_cycle = options.ports, 240 ruby_system = ruby_system) 241 242 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 243 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) --- 36 unchanged lines hidden --- |