1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# Copyright (c) 2013 Mark D. Hill and David A. Wood 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 103 unchanged lines hidden (view full) --- 112 l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, 113 start_index_bit = block_size_bits, is_icache = False) 114 115 l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j, 116 cache = l1_cache, l2_select_num_bits = l2_bits, 117 cluster_id = i, ruby_system = ruby_system) 118 119 if piobus != None: |
120 cpu_seq.pio_master_port = piobus.slave 121 cpu_seq.mem_master_port = piobus.slave 122 cpu_seq.pio_slave_port = piobus.master |
123 124 exec("ruby_system.l0_cntrl%d = l0_cntrl" % ( 125 i*num_cpus_per_cluster+j)) 126 exec("ruby_system.l1_cntrl%d = l1_cntrl" % ( 127 i*num_cpus_per_cluster+j)) 128 129 # 130 # Add controllers and sequencers to the appropriate lists --- 82 unchanged lines hidden --- |