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< # Copyright (c) 2009 Advanced Micro Devices, Inc.
---
> # Copyright (c) 2009,2015 Advanced Micro Devices, Inc.
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< parser.add_option("--num-clusters", type="int", default=1,
< help="number of clusters in a design in which there are shared\
---
> parser.add_option("--num-clusters", type = "int", default = 1,
> help = "number of clusters in a design in which there are shared\
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< fatal("This script requires the MESI_Three_Level protocol to be built.")
---
> fatal("This script requires the MESI_Three_Level protocol to be\
> built.")
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< # consistent with the NetDest list. Therefore the l1 controller nodes must be
< # listed before the directory nodes and directory nodes before dma nodes, etc.
---
> # consistent with the NetDest list. Therefore the l1 controller nodes
> # must be listed before the directory nodes and directory nodes before
> # dma nodes, etc.
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< l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j,
< Icache = l0i_cache, Dcache = l0d_cache,
< send_evictions = send_evicts(options),
< clk_domain=system.cpu[i].clk_domain,
< ruby_system = ruby_system)
---
> # the ruby random tester reuses num_cpus to specify the
> # number of cpu ports connected to the tester object, which
> # is stored in system.cpu. because there is only ever one
> # tester object, num_cpus is not necessarily equal to the
> # size of system.cpu; therefore if len(system.cpu) == 1
> # we use system.cpu[0] to set the clk_domain, thereby ensuring
> # we don't index off the end of the cpu list.
> if len(system.cpu) == 1:
> clk_domain = system.cpu[0].clk_domain
> else:
> clk_domain = system.cpu[i].clk_domain
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> l0_cntrl = L0Cache_Controller(
> version = i * num_cpus_per_cluster + j, Icache = l0i_cache,
> Dcache = l0d_cache, send_evictions = send_evicts(options),
> clk_domain = clk_domain, ruby_system = ruby_system)
>
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< icache = l0i_cache,
< clk_domain=system.cpu[i].clk_domain,
< dcache = l0d_cache, ruby_system = ruby_system)
---
> icache = l0i_cache,
> clk_domain = clk_domain,
> dcache = l0d_cache,
> ruby_system = ruby_system)
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< l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc,
< start_index_bit = block_size_bits, is_icache = False)
---
> l1_cache = L1Cache(size = options.l1d_size,
> assoc = options.l1d_assoc,
> start_index_bit = block_size_bits,
> is_icache = False)
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< l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j,
< cache = l1_cache, l2_select_num_bits = l2_bits,
< cluster_id = i, ruby_system = ruby_system)
---
> l1_cntrl = L1Cache_Controller(
> version = i * num_cpus_per_cluster + j,
> cache = l1_cache, l2_select_num_bits = l2_bits,
> cluster_id = i, ruby_system = ruby_system)
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< exec("ruby_system.l0_cntrl%d = l0_cntrl" % (
< i*num_cpus_per_cluster+j))
< exec("ruby_system.l1_cntrl%d = l1_cntrl" % (
< i*num_cpus_per_cluster+j))
---
> exec("ruby_system.l0_cntrl%d = l0_cntrl"
> % ( i * num_cpus_per_cluster + j))
> exec("ruby_system.l1_cntrl%d = l1_cntrl"
> % ( i * num_cpus_per_cluster + j))
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< transitions_per_cycle=options.ports,
---
> transitions_per_cycle = options.ports,
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< exec("ruby_system.l2_cntrl%d = l2_cntrl" % (
< i * num_l2caches_per_cluster + j))
---
> exec("ruby_system.l2_cntrl%d = l2_cntrl"
> % (i * num_l2caches_per_cluster + j))
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< clk_domain=ruby_system.clk_domain,
< clk_divider=3)
---
> clk_domain = ruby_system.clk_domain, clk_divider = 3)
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< directory = RubyDirectoryMemory(
< version = i, size = dir_size),
< transitions_per_cycle = options.ports,
< ruby_system = ruby_system)
---
> directory = RubyDirectoryMemory(version = i, size = dir_size),
> transitions_per_cycle = options.ports,
> ruby_system = ruby_system)
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< dma_seq = DMASequencer(version = i,
< ruby_system = ruby_system)
---
> dma_seq = DMASequencer(version = i, ruby_system = ruby_system)