1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# Copyright (c) 2013 Mark D. Hill and David A. Wood
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Brad Beckmann
30# Nilay Vaish
31
32import math
33import m5
34from m5.objects import *
35from m5.defines import buildEnv
36from Ruby import create_topology
37from Ruby import send_evicts
38
39#
40# Note: the L1 Cache latency is only used by the sequencer on fast path hits
41#
42class L0Cache(RubyCache):
43 latency = 1
44
45class L1Cache(RubyCache):
46 latency = 5
47
48#
49# Note: the L2 Cache latency is not currently used
50#
51class L2Cache(RubyCache):
52 latency = 15
53
54def define_options(parser):
55 parser.add_option("--num-clusters", type="int", default=1,
56 help="number of clusters in a design in which there are shared\
57 caches private to clusters")
58 return
59
60def create_system(options, full_system, system, dma_ports, ruby_system):
61
62 if buildEnv['PROTOCOL'] != 'MESI_Three_Level':
63 fatal("This script requires the MESI_Three_Level protocol to be built.")
64
65 cpu_sequencers = []
66
67 #
68 # The ruby network creation expects the list of nodes in the system to be
69 # consistent with the NetDest list. Therefore the l1 controller nodes must be
70 # listed before the directory nodes and directory nodes before dma nodes, etc.
71 #
72 l0_cntrl_nodes = []
73 l1_cntrl_nodes = []
74 l2_cntrl_nodes = []
75 dir_cntrl_nodes = []
76 dma_cntrl_nodes = []
77
78 assert (options.num_cpus % options.num_clusters == 0)
79 num_cpus_per_cluster = options.num_cpus / options.num_clusters
80
81 assert (options.num_l2caches % options.num_clusters == 0)
82 num_l2caches_per_cluster = options.num_l2caches / options.num_clusters
83
84 l2_bits = int(math.log(num_l2caches_per_cluster, 2))
85 block_size_bits = int(math.log(options.cacheline_size, 2))
86 l2_index_start = block_size_bits + l2_bits
87
88 #
89 # Must create the individual controllers before the network to ensure the
90 # controller constructors are called before the network constructor
91 #
92 for i in xrange(options.num_clusters):
93 for j in xrange(num_cpus_per_cluster):
94 #
95 # First create the Ruby objects associated with this cpu
96 #
97 l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True,
98 start_index_bit = block_size_bits,
99 replacement_policy = LRUReplacementPolicy())
100
101 l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False,
102 start_index_bit = block_size_bits,
103 replacement_policy = LRUReplacementPolicy())
104
105 l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j,
106 Icache = l0i_cache, Dcache = l0d_cache,
107 send_evictions = send_evicts(options),
108 clk_domain=system.cpu[i].clk_domain,
109 ruby_system = ruby_system)
110
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# Copyright (c) 2013 Mark D. Hill and David A. Wood
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Brad Beckmann
30# Nilay Vaish
31
32import math
33import m5
34from m5.objects import *
35from m5.defines import buildEnv
36from Ruby import create_topology
37from Ruby import send_evicts
38
39#
40# Note: the L1 Cache latency is only used by the sequencer on fast path hits
41#
42class L0Cache(RubyCache):
43 latency = 1
44
45class L1Cache(RubyCache):
46 latency = 5
47
48#
49# Note: the L2 Cache latency is not currently used
50#
51class L2Cache(RubyCache):
52 latency = 15
53
54def define_options(parser):
55 parser.add_option("--num-clusters", type="int", default=1,
56 help="number of clusters in a design in which there are shared\
57 caches private to clusters")
58 return
59
60def create_system(options, full_system, system, dma_ports, ruby_system):
61
62 if buildEnv['PROTOCOL'] != 'MESI_Three_Level':
63 fatal("This script requires the MESI_Three_Level protocol to be built.")
64
65 cpu_sequencers = []
66
67 #
68 # The ruby network creation expects the list of nodes in the system to be
69 # consistent with the NetDest list. Therefore the l1 controller nodes must be
70 # listed before the directory nodes and directory nodes before dma nodes, etc.
71 #
72 l0_cntrl_nodes = []
73 l1_cntrl_nodes = []
74 l2_cntrl_nodes = []
75 dir_cntrl_nodes = []
76 dma_cntrl_nodes = []
77
78 assert (options.num_cpus % options.num_clusters == 0)
79 num_cpus_per_cluster = options.num_cpus / options.num_clusters
80
81 assert (options.num_l2caches % options.num_clusters == 0)
82 num_l2caches_per_cluster = options.num_l2caches / options.num_clusters
83
84 l2_bits = int(math.log(num_l2caches_per_cluster, 2))
85 block_size_bits = int(math.log(options.cacheline_size, 2))
86 l2_index_start = block_size_bits + l2_bits
87
88 #
89 # Must create the individual controllers before the network to ensure the
90 # controller constructors are called before the network constructor
91 #
92 for i in xrange(options.num_clusters):
93 for j in xrange(num_cpus_per_cluster):
94 #
95 # First create the Ruby objects associated with this cpu
96 #
97 l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True,
98 start_index_bit = block_size_bits,
99 replacement_policy = LRUReplacementPolicy())
100
101 l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False,
102 start_index_bit = block_size_bits,
103 replacement_policy = LRUReplacementPolicy())
104
105 l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j,
106 Icache = l0i_cache, Dcache = l0d_cache,
107 send_evictions = send_evicts(options),
108 clk_domain=system.cpu[i].clk_domain,
109 ruby_system = ruby_system)
110
|
112 clk_domain=system.cpu[i].clk_domain,
113 dcache = l0d_cache, ruby_system = ruby_system)
114
115 l0_cntrl.sequencer = cpu_seq
116
117 l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc,
118 start_index_bit = block_size_bits, is_icache = False)
119
120 l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j,
121 cache = l1_cache, l2_select_num_bits = l2_bits,
122 cluster_id = i, ruby_system = ruby_system)
123
124 exec("ruby_system.l0_cntrl%d = l0_cntrl" % (
125 i*num_cpus_per_cluster+j))
126 exec("ruby_system.l1_cntrl%d = l1_cntrl" % (
127 i*num_cpus_per_cluster+j))
128
129 #
130 # Add controllers and sequencers to the appropriate lists
131 #
132 cpu_sequencers.append(cpu_seq)
133 l0_cntrl_nodes.append(l0_cntrl)
134 l1_cntrl_nodes.append(l1_cntrl)
135
136 # Connect the L0 and L1 controllers
137 l0_cntrl.bufferToL1 = l1_cntrl.bufferFromL0
138 l0_cntrl.bufferFromL1 = l1_cntrl.bufferToL0
139
140 # Connect the L1 controllers and the network
141 l1_cntrl.requestToL2 = ruby_system.network.slave
142 l1_cntrl.responseToL2 = ruby_system.network.slave
143 l1_cntrl.unblockToL2 = ruby_system.network.slave
144
145 l1_cntrl.requestFromL2 = ruby_system.network.master
146 l1_cntrl.responseFromL2 = ruby_system.network.master
147
148
149 for j in xrange(num_l2caches_per_cluster):
150 l2_cache = L2Cache(size = options.l2_size,
151 assoc = options.l2_assoc,
152 start_index_bit = l2_index_start)
153
154 l2_cntrl = L2Cache_Controller(
155 version = i * num_l2caches_per_cluster + j,
156 L2cache = l2_cache, cluster_id = i,
157 transitions_per_cycle=options.ports,
158 ruby_system = ruby_system)
159
160 exec("ruby_system.l2_cntrl%d = l2_cntrl" % (
161 i * num_l2caches_per_cluster + j))
162 l2_cntrl_nodes.append(l2_cntrl)
163
164 # Connect the L2 controllers and the network
165 l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave
166 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
167 l2_cntrl.responseFromL2Cache = ruby_system.network.slave
168
169 l2_cntrl.unblockToL2Cache = ruby_system.network.master
170 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
171 l2_cntrl.responseToL2Cache = ruby_system.network.master
172
173 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
174 assert(phys_mem_size % options.num_dirs == 0)
175 mem_module_size = phys_mem_size / options.num_dirs
176
177 # Run each of the ruby memory controllers at a ratio of the frequency of
178 # the ruby system
179 # clk_divider value is a fix to pass regression.
180 ruby_system.memctrl_clk_domain = DerivedClockDomain(
181 clk_domain=ruby_system.clk_domain,
182 clk_divider=3)
183
184 for i in xrange(options.num_dirs):
185 #
186 # Create the Ruby objects associated with the directory controller
187 #
188 dir_size = MemorySize('0B')
189 dir_size.value = mem_module_size
190
191 dir_cntrl = Directory_Controller(version = i,
192 directory = RubyDirectoryMemory(
193 version = i, size = dir_size),
194 transitions_per_cycle = options.ports,
195 ruby_system = ruby_system)
196
197 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
198 dir_cntrl_nodes.append(dir_cntrl)
199
200 # Connect the directory controllers and the network
201 dir_cntrl.requestToDir = ruby_system.network.master
202 dir_cntrl.responseToDir = ruby_system.network.master
203 dir_cntrl.responseFromDir = ruby_system.network.slave
204
205 for i, dma_port in enumerate(dma_ports):
206 #
207 # Create the Ruby objects associated with the dma controller
208 #
209 dma_seq = DMASequencer(version = i,
210 ruby_system = ruby_system)
211
212 dma_cntrl = DMA_Controller(version = i,
213 dma_sequencer = dma_seq,
214 transitions_per_cycle = options.ports,
215 ruby_system = ruby_system)
216
217 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
218 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
219 dma_cntrl_nodes.append(dma_cntrl)
220
221 # Connect the dma controller to the network
222 dma_cntrl.responseFromDir = ruby_system.network.master
223 dma_cntrl.requestToDir = ruby_system.network.slave
224
225 all_cntrls = l0_cntrl_nodes + \
226 l1_cntrl_nodes + \
227 l2_cntrl_nodes + \
228 dir_cntrl_nodes + \
229 dma_cntrl_nodes
230
231 # Create the io controller and the sequencer
232 if full_system:
233 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
234 ruby_system._io_port = io_seq
235 io_controller = DMA_Controller(version = len(dma_ports),
236 dma_sequencer = io_seq,
237 ruby_system = ruby_system)
238 ruby_system.io_controller = io_controller
239
240 # Connect the dma controller to the network
241 io_controller.responseFromDir = ruby_system.network.master
242 io_controller.requestToDir = ruby_system.network.slave
243
244 all_cntrls = all_cntrls + [io_controller]
245
246 topology = create_topology(all_cntrls, options)
247 return (cpu_sequencers, dir_cntrl_nodes, topology)
| 113 clk_domain=system.cpu[i].clk_domain,
114 dcache = l0d_cache, ruby_system = ruby_system)
115
116 l0_cntrl.sequencer = cpu_seq
117
118 l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc,
119 start_index_bit = block_size_bits, is_icache = False)
120
121 l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j,
122 cache = l1_cache, l2_select_num_bits = l2_bits,
123 cluster_id = i, ruby_system = ruby_system)
124
125 exec("ruby_system.l0_cntrl%d = l0_cntrl" % (
126 i*num_cpus_per_cluster+j))
127 exec("ruby_system.l1_cntrl%d = l1_cntrl" % (
128 i*num_cpus_per_cluster+j))
129
130 #
131 # Add controllers and sequencers to the appropriate lists
132 #
133 cpu_sequencers.append(cpu_seq)
134 l0_cntrl_nodes.append(l0_cntrl)
135 l1_cntrl_nodes.append(l1_cntrl)
136
137 # Connect the L0 and L1 controllers
138 l0_cntrl.bufferToL1 = l1_cntrl.bufferFromL0
139 l0_cntrl.bufferFromL1 = l1_cntrl.bufferToL0
140
141 # Connect the L1 controllers and the network
142 l1_cntrl.requestToL2 = ruby_system.network.slave
143 l1_cntrl.responseToL2 = ruby_system.network.slave
144 l1_cntrl.unblockToL2 = ruby_system.network.slave
145
146 l1_cntrl.requestFromL2 = ruby_system.network.master
147 l1_cntrl.responseFromL2 = ruby_system.network.master
148
149
150 for j in xrange(num_l2caches_per_cluster):
151 l2_cache = L2Cache(size = options.l2_size,
152 assoc = options.l2_assoc,
153 start_index_bit = l2_index_start)
154
155 l2_cntrl = L2Cache_Controller(
156 version = i * num_l2caches_per_cluster + j,
157 L2cache = l2_cache, cluster_id = i,
158 transitions_per_cycle=options.ports,
159 ruby_system = ruby_system)
160
161 exec("ruby_system.l2_cntrl%d = l2_cntrl" % (
162 i * num_l2caches_per_cluster + j))
163 l2_cntrl_nodes.append(l2_cntrl)
164
165 # Connect the L2 controllers and the network
166 l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave
167 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
168 l2_cntrl.responseFromL2Cache = ruby_system.network.slave
169
170 l2_cntrl.unblockToL2Cache = ruby_system.network.master
171 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
172 l2_cntrl.responseToL2Cache = ruby_system.network.master
173
174 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
175 assert(phys_mem_size % options.num_dirs == 0)
176 mem_module_size = phys_mem_size / options.num_dirs
177
178 # Run each of the ruby memory controllers at a ratio of the frequency of
179 # the ruby system
180 # clk_divider value is a fix to pass regression.
181 ruby_system.memctrl_clk_domain = DerivedClockDomain(
182 clk_domain=ruby_system.clk_domain,
183 clk_divider=3)
184
185 for i in xrange(options.num_dirs):
186 #
187 # Create the Ruby objects associated with the directory controller
188 #
189 dir_size = MemorySize('0B')
190 dir_size.value = mem_module_size
191
192 dir_cntrl = Directory_Controller(version = i,
193 directory = RubyDirectoryMemory(
194 version = i, size = dir_size),
195 transitions_per_cycle = options.ports,
196 ruby_system = ruby_system)
197
198 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
199 dir_cntrl_nodes.append(dir_cntrl)
200
201 # Connect the directory controllers and the network
202 dir_cntrl.requestToDir = ruby_system.network.master
203 dir_cntrl.responseToDir = ruby_system.network.master
204 dir_cntrl.responseFromDir = ruby_system.network.slave
205
206 for i, dma_port in enumerate(dma_ports):
207 #
208 # Create the Ruby objects associated with the dma controller
209 #
210 dma_seq = DMASequencer(version = i,
211 ruby_system = ruby_system)
212
213 dma_cntrl = DMA_Controller(version = i,
214 dma_sequencer = dma_seq,
215 transitions_per_cycle = options.ports,
216 ruby_system = ruby_system)
217
218 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
219 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
220 dma_cntrl_nodes.append(dma_cntrl)
221
222 # Connect the dma controller to the network
223 dma_cntrl.responseFromDir = ruby_system.network.master
224 dma_cntrl.requestToDir = ruby_system.network.slave
225
226 all_cntrls = l0_cntrl_nodes + \
227 l1_cntrl_nodes + \
228 l2_cntrl_nodes + \
229 dir_cntrl_nodes + \
230 dma_cntrl_nodes
231
232 # Create the io controller and the sequencer
233 if full_system:
234 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
235 ruby_system._io_port = io_seq
236 io_controller = DMA_Controller(version = len(dma_ports),
237 dma_sequencer = io_seq,
238 ruby_system = ruby_system)
239 ruby_system.io_controller = io_controller
240
241 # Connect the dma controller to the network
242 io_controller.responseFromDir = ruby_system.network.master
243 io_controller.requestToDir = ruby_system.network.slave
244
245 all_cntrls = all_cntrls + [io_controller]
246
247 topology = create_topology(all_cntrls, options)
248 return (cpu_sequencers, dir_cntrl_nodes, topology)
|