1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# Copyright (c) 2013 Mark D. Hill and David A. Wood
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Brad Beckmann
30# Nilay Vaish
31
32import math
33import m5
34from m5.objects import *
35from m5.defines import buildEnv
36from Ruby import create_topology
37
38#
39# Note: the L1 Cache latency is only used by the sequencer on fast path hits
40#
41class L0Cache(RubyCache):
42 latency = 1
43
44class L1Cache(RubyCache):
45 latency = 5
46
47#
48# Note: the L2 Cache latency is not currently used
49#
50class L2Cache(RubyCache):
51 latency = 15
52
53def define_options(parser):
54 parser.add_option("--num-clusters", type="int", default=1,
55 help="number of clusters in a design in which there are shared\
56 caches private to clusters")
57 return
58
59def create_system(options, full_system, system, dma_ports, ruby_system):
60
61 if buildEnv['PROTOCOL'] != 'MESI_Three_Level':
62 fatal("This script requires the MESI_Three_Level protocol to be built.")
63
64 cpu_sequencers = []
65
66 #
67 # The ruby network creation expects the list of nodes in the system to be
68 # consistent with the NetDest list. Therefore the l1 controller nodes must be
69 # listed before the directory nodes and directory nodes before dma nodes, etc.
70 #
71 l0_cntrl_nodes = []
72 l1_cntrl_nodes = []
73 l2_cntrl_nodes = []
74 dir_cntrl_nodes = []
75 dma_cntrl_nodes = []
76
77 assert (options.num_cpus % options.num_clusters == 0)
78 num_cpus_per_cluster = options.num_cpus / options.num_clusters
79
80 assert (options.num_l2caches % options.num_clusters == 0)
81 num_l2caches_per_cluster = options.num_l2caches / options.num_clusters
82
83 l2_bits = int(math.log(num_l2caches_per_cluster, 2))
84 block_size_bits = int(math.log(options.cacheline_size, 2))
85 l2_index_start = block_size_bits + l2_bits
86
87 #
88 # Must create the individual controllers before the network to ensure the
89 # controller constructors are called before the network constructor
90 #
91 for i in xrange(options.num_clusters):
92 for j in xrange(num_cpus_per_cluster):
93 #
94 # First create the Ruby objects associated with this cpu
95 #
96 l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True,
97 start_index_bit = block_size_bits, replacement_policy="LRU")
98
99 l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False,
100 start_index_bit = block_size_bits, replacement_policy="LRU")
101
102 l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j,
103 Icache = l0i_cache, Dcache = l0d_cache,
104 send_evictions = (options.cpu_type == "detailed"),
105 clk_domain=system.cpu[i].clk_domain,
106 ruby_system = ruby_system)
107
108 cpu_seq = RubySequencer(version = i, icache = l0i_cache,
109 clk_domain=system.cpu[i].clk_domain,
110 dcache = l0d_cache, ruby_system = ruby_system)
111
112 l0_cntrl.sequencer = cpu_seq
113
114 l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc,
115 start_index_bit = block_size_bits, is_icache = False)
116
117 l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j,
118 cache = l1_cache, l2_select_num_bits = l2_bits,
119 cluster_id = i, ruby_system = ruby_system)
120
121 exec("ruby_system.l0_cntrl%d = l0_cntrl" % (
122 i*num_cpus_per_cluster+j))
123 exec("ruby_system.l1_cntrl%d = l1_cntrl" % (
124 i*num_cpus_per_cluster+j))
125
126 #
127 # Add controllers and sequencers to the appropriate lists
128 #
129 cpu_sequencers.append(cpu_seq)
130 l0_cntrl_nodes.append(l0_cntrl)
131 l1_cntrl_nodes.append(l1_cntrl)
132
133 # Connect the L0 and L1 controllers
134 l0_cntrl.bufferToL1 = l1_cntrl.bufferFromL0
135 l0_cntrl.bufferFromL1 = l1_cntrl.bufferToL0
136
137 # Connect the L1 controllers and the network
138 l1_cntrl.requestToL2 = ruby_system.network.slave
139 l1_cntrl.responseToL2 = ruby_system.network.slave
140 l1_cntrl.unblockToL2 = ruby_system.network.slave
141
142 l1_cntrl.requestFromL2 = ruby_system.network.master
143 l1_cntrl.responseFromL2 = ruby_system.network.master
144
145
146 for j in xrange(num_l2caches_per_cluster):
147 l2_cache = L2Cache(size = options.l2_size,
148 assoc = options.l2_assoc,
149 start_index_bit = l2_index_start)
150
151 l2_cntrl = L2Cache_Controller(
152 version = i * num_l2caches_per_cluster + j,
153 L2cache = l2_cache, cluster_id = i,
154 transitions_per_cycle=options.ports,
155 ruby_system = ruby_system)
156
157 exec("ruby_system.l2_cntrl%d = l2_cntrl" % (
158 i * num_l2caches_per_cluster + j))
159 l2_cntrl_nodes.append(l2_cntrl)
160
161 # Connect the L2 controllers and the network
162 l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave
163 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
164 l2_cntrl.responseFromL2Cache = ruby_system.network.slave
165
166 l2_cntrl.unblockToL2Cache = ruby_system.network.master
167 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
168 l2_cntrl.responseToL2Cache = ruby_system.network.master
169
170 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
171 assert(phys_mem_size % options.num_dirs == 0)
172 mem_module_size = phys_mem_size / options.num_dirs
173
174 # Run each of the ruby memory controllers at a ratio of the frequency of
175 # the ruby system
176 # clk_divider value is a fix to pass regression.
177 ruby_system.memctrl_clk_domain = DerivedClockDomain(
178 clk_domain=ruby_system.clk_domain,
179 clk_divider=3)
180
181 for i in xrange(options.num_dirs):
182 #
183 # Create the Ruby objects associated with the directory controller
184 #
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# Copyright (c) 2013 Mark D. Hill and David A. Wood
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Brad Beckmann
30# Nilay Vaish
31
32import math
33import m5
34from m5.objects import *
35from m5.defines import buildEnv
36from Ruby import create_topology
37
38#
39# Note: the L1 Cache latency is only used by the sequencer on fast path hits
40#
41class L0Cache(RubyCache):
42 latency = 1
43
44class L1Cache(RubyCache):
45 latency = 5
46
47#
48# Note: the L2 Cache latency is not currently used
49#
50class L2Cache(RubyCache):
51 latency = 15
52
53def define_options(parser):
54 parser.add_option("--num-clusters", type="int", default=1,
55 help="number of clusters in a design in which there are shared\
56 caches private to clusters")
57 return
58
59def create_system(options, full_system, system, dma_ports, ruby_system):
60
61 if buildEnv['PROTOCOL'] != 'MESI_Three_Level':
62 fatal("This script requires the MESI_Three_Level protocol to be built.")
63
64 cpu_sequencers = []
65
66 #
67 # The ruby network creation expects the list of nodes in the system to be
68 # consistent with the NetDest list. Therefore the l1 controller nodes must be
69 # listed before the directory nodes and directory nodes before dma nodes, etc.
70 #
71 l0_cntrl_nodes = []
72 l1_cntrl_nodes = []
73 l2_cntrl_nodes = []
74 dir_cntrl_nodes = []
75 dma_cntrl_nodes = []
76
77 assert (options.num_cpus % options.num_clusters == 0)
78 num_cpus_per_cluster = options.num_cpus / options.num_clusters
79
80 assert (options.num_l2caches % options.num_clusters == 0)
81 num_l2caches_per_cluster = options.num_l2caches / options.num_clusters
82
83 l2_bits = int(math.log(num_l2caches_per_cluster, 2))
84 block_size_bits = int(math.log(options.cacheline_size, 2))
85 l2_index_start = block_size_bits + l2_bits
86
87 #
88 # Must create the individual controllers before the network to ensure the
89 # controller constructors are called before the network constructor
90 #
91 for i in xrange(options.num_clusters):
92 for j in xrange(num_cpus_per_cluster):
93 #
94 # First create the Ruby objects associated with this cpu
95 #
96 l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True,
97 start_index_bit = block_size_bits, replacement_policy="LRU")
98
99 l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False,
100 start_index_bit = block_size_bits, replacement_policy="LRU")
101
102 l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j,
103 Icache = l0i_cache, Dcache = l0d_cache,
104 send_evictions = (options.cpu_type == "detailed"),
105 clk_domain=system.cpu[i].clk_domain,
106 ruby_system = ruby_system)
107
108 cpu_seq = RubySequencer(version = i, icache = l0i_cache,
109 clk_domain=system.cpu[i].clk_domain,
110 dcache = l0d_cache, ruby_system = ruby_system)
111
112 l0_cntrl.sequencer = cpu_seq
113
114 l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc,
115 start_index_bit = block_size_bits, is_icache = False)
116
117 l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j,
118 cache = l1_cache, l2_select_num_bits = l2_bits,
119 cluster_id = i, ruby_system = ruby_system)
120
121 exec("ruby_system.l0_cntrl%d = l0_cntrl" % (
122 i*num_cpus_per_cluster+j))
123 exec("ruby_system.l1_cntrl%d = l1_cntrl" % (
124 i*num_cpus_per_cluster+j))
125
126 #
127 # Add controllers and sequencers to the appropriate lists
128 #
129 cpu_sequencers.append(cpu_seq)
130 l0_cntrl_nodes.append(l0_cntrl)
131 l1_cntrl_nodes.append(l1_cntrl)
132
133 # Connect the L0 and L1 controllers
134 l0_cntrl.bufferToL1 = l1_cntrl.bufferFromL0
135 l0_cntrl.bufferFromL1 = l1_cntrl.bufferToL0
136
137 # Connect the L1 controllers and the network
138 l1_cntrl.requestToL2 = ruby_system.network.slave
139 l1_cntrl.responseToL2 = ruby_system.network.slave
140 l1_cntrl.unblockToL2 = ruby_system.network.slave
141
142 l1_cntrl.requestFromL2 = ruby_system.network.master
143 l1_cntrl.responseFromL2 = ruby_system.network.master
144
145
146 for j in xrange(num_l2caches_per_cluster):
147 l2_cache = L2Cache(size = options.l2_size,
148 assoc = options.l2_assoc,
149 start_index_bit = l2_index_start)
150
151 l2_cntrl = L2Cache_Controller(
152 version = i * num_l2caches_per_cluster + j,
153 L2cache = l2_cache, cluster_id = i,
154 transitions_per_cycle=options.ports,
155 ruby_system = ruby_system)
156
157 exec("ruby_system.l2_cntrl%d = l2_cntrl" % (
158 i * num_l2caches_per_cluster + j))
159 l2_cntrl_nodes.append(l2_cntrl)
160
161 # Connect the L2 controllers and the network
162 l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave
163 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
164 l2_cntrl.responseFromL2Cache = ruby_system.network.slave
165
166 l2_cntrl.unblockToL2Cache = ruby_system.network.master
167 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
168 l2_cntrl.responseToL2Cache = ruby_system.network.master
169
170 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
171 assert(phys_mem_size % options.num_dirs == 0)
172 mem_module_size = phys_mem_size / options.num_dirs
173
174 # Run each of the ruby memory controllers at a ratio of the frequency of
175 # the ruby system
176 # clk_divider value is a fix to pass regression.
177 ruby_system.memctrl_clk_domain = DerivedClockDomain(
178 clk_domain=ruby_system.clk_domain,
179 clk_divider=3)
180
181 for i in xrange(options.num_dirs):
182 #
183 # Create the Ruby objects associated with the directory controller
184 #
|
201 transitions_per_cycle = options.ports,
202 ruby_system = ruby_system)
203
204 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
205 dir_cntrl_nodes.append(dir_cntrl)
206
207 # Connect the directory controllers and the network
208 dir_cntrl.requestToDir = ruby_system.network.master
209 dir_cntrl.responseToDir = ruby_system.network.master
210 dir_cntrl.responseFromDir = ruby_system.network.slave
211
212 for i, dma_port in enumerate(dma_ports):
213 #
214 # Create the Ruby objects associated with the dma controller
215 #
216 dma_seq = DMASequencer(version = i,
217 ruby_system = ruby_system)
218
219 dma_cntrl = DMA_Controller(version = i,
220 dma_sequencer = dma_seq,
221 transitions_per_cycle = options.ports,
222 ruby_system = ruby_system)
223
224 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
225 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
226 dma_cntrl_nodes.append(dma_cntrl)
227
228 all_cntrls = l0_cntrl_nodes + \
229 l1_cntrl_nodes + \
230 l2_cntrl_nodes + \
231 dir_cntrl_nodes + \
232 dma_cntrl_nodes
233
234 # Create the io controller and the sequencer
235 if full_system:
236 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
237 ruby_system._io_port = io_seq
238 io_controller = DMA_Controller(version = len(dma_ports),
239 dma_sequencer = io_seq,
240 ruby_system = ruby_system)
241 ruby_system.io_controller = io_controller
242
243 # Connect the dma controller to the network
244 io_controller.responseFromDir = ruby_system.network.master
245 io_controller.requestToDir = ruby_system.network.slave
246
247 all_cntrls = all_cntrls + [io_controller]
248
249 topology = create_topology(all_cntrls, options)
250 return (cpu_sequencers, dir_cntrl_nodes, topology)
| 191 transitions_per_cycle = options.ports,
192 ruby_system = ruby_system)
193
194 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
195 dir_cntrl_nodes.append(dir_cntrl)
196
197 # Connect the directory controllers and the network
198 dir_cntrl.requestToDir = ruby_system.network.master
199 dir_cntrl.responseToDir = ruby_system.network.master
200 dir_cntrl.responseFromDir = ruby_system.network.slave
201
202 for i, dma_port in enumerate(dma_ports):
203 #
204 # Create the Ruby objects associated with the dma controller
205 #
206 dma_seq = DMASequencer(version = i,
207 ruby_system = ruby_system)
208
209 dma_cntrl = DMA_Controller(version = i,
210 dma_sequencer = dma_seq,
211 transitions_per_cycle = options.ports,
212 ruby_system = ruby_system)
213
214 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
215 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
216 dma_cntrl_nodes.append(dma_cntrl)
217
218 all_cntrls = l0_cntrl_nodes + \
219 l1_cntrl_nodes + \
220 l2_cntrl_nodes + \
221 dir_cntrl_nodes + \
222 dma_cntrl_nodes
223
224 # Create the io controller and the sequencer
225 if full_system:
226 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
227 ruby_system._io_port = io_seq
228 io_controller = DMA_Controller(version = len(dma_ports),
229 dma_sequencer = io_seq,
230 ruby_system = ruby_system)
231 ruby_system.io_controller = io_controller
232
233 # Connect the dma controller to the network
234 io_controller.responseFromDir = ruby_system.network.master
235 io_controller.requestToDir = ruby_system.network.slave
236
237 all_cntrls = all_cntrls + [io_controller]
238
239 topology = create_topology(all_cntrls, options)
240 return (cpu_sequencers, dir_cntrl_nodes, topology)
|